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Date: Thu, 21 Dec 2017 18:11:13 -0800
From: Stephen Boyd <sboyd@codeaurora.org>
To: Sergej Sawazki <sergej@taudac.com>
Cc: mturquette@baylibre.com, sebastian.hesselbarth@gmail.com,
	linux@armlinux.org.uk, linux-clk@vger.kernel.org, ce3a@gmx.de,
	Rabeeh Khoury <rabeeh@solid-run.com>
Subject: Re: [PATCH v2 1/2] clk: si5351: Add DT property to enable PLL reset
Message-ID: <20171222021113.GM7997@codeaurora.org>
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 <1505562282-9111-2-git-send-email-sergej@taudac.com>
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On 09/16, Sergej Sawazki wrote:
> Add optional output clock DT property to enable PLL reset when a clock
> output is enabled.
> 
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Cc: Rabeeh Khoury <rabeeh@solid-run.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Signed-off-by: Sergej Sawazki <sergej@taudac.com>
> ---

Applied to clk-next

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