* [PATCH v2 1/2] clk: si5351: Add DT property to enable PLL reset
2017-09-16 11:44 [PATCH v2 0/2] clk: si5351: PLL reset fixes Sergej Sawazki
@ 2017-09-16 11:44 ` Sergej Sawazki
2017-12-22 2:11 ` Stephen Boyd
2017-09-16 11:44 ` [PATCH v2 2/2] clk: si5351: Apply PLL soft reset before enabling the outputs Sergej Sawazki
1 sibling, 1 reply; 5+ messages in thread
From: Sergej Sawazki @ 2017-09-16 11:44 UTC (permalink / raw)
To: sboyd, mturquette, sebastian.hesselbarth
Cc: linux, linux-clk, ce3a, Sergej Sawazki, Rabeeh Khoury
Add optional output clock DT property to enable PLL reset when a clock
output is enabled.
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
---
Documentation/devicetree/bindings/clock/silabs,si5351.txt | 1 +
drivers/clk/clk-si5351.c | 3 +++
include/linux/platform_data/si5351.h | 2 ++
3 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
index 28b2830..157ee02 100644
--- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt
+++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
@@ -45,6 +45,7 @@ Optional child node properties:
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
+- silabs,pll-reset: boolean, clock output can reset its pll.
- silabs,disable-state : clock output disable state, shall be
0 = clock output is driven LOW when disabled
1 = clock output is driven HIGH when disabled
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 20d9076..aba2895 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1297,6 +1297,9 @@ static int si5351_dt_parse(struct i2c_client *client,
pdata->clkout[num].pll_master =
of_property_read_bool(child, "silabs,pll-master");
+
+ pdata->clkout[num].pll_reset =
+ of_property_read_bool(child, "silabs,pll-reset");
}
client->dev.platform_data = pdata;
diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h
index 533d980..da346f22 100644
--- a/include/linux/platform_data/si5351.h
+++ b/include/linux/platform_data/si5351.h
@@ -85,6 +85,7 @@ enum si5351_disable_state {
* @multisynth_src: multisynth source clock
* @clkout_src: clkout source clock
* @pll_master: if true, clkout can also change pll rate
+ * @pll_reset: if true, clkout can reset its pll
* @drive: output drive strength
* @rate: initial clkout rate, or default if 0
*/
@@ -94,6 +95,7 @@ struct si5351_clkout_config {
enum si5351_drive_strength drive;
enum si5351_disable_state disable_state;
bool pll_master;
+ bool pll_reset;
unsigned long rate;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/2] clk: si5351: Apply PLL soft reset before enabling the outputs
2017-09-16 11:44 [PATCH v2 0/2] clk: si5351: PLL reset fixes Sergej Sawazki
2017-09-16 11:44 ` [PATCH v2 1/2] clk: si5351: Add DT property to enable PLL reset Sergej Sawazki
@ 2017-09-16 11:44 ` Sergej Sawazki
2017-12-22 2:11 ` Stephen Boyd
1 sibling, 1 reply; 5+ messages in thread
From: Sergej Sawazki @ 2017-09-16 11:44 UTC (permalink / raw)
To: sboyd, mturquette, sebastian.hesselbarth
Cc: linux, linux-clk, ce3a, Sergej Sawazki, Rabeeh Khoury
The "Si5351A/B/C Data Sheet" states to apply a PLL soft reset before
enabling the output clocks [1]. This is required to get a deterministic
phase relationship between the output clocks.
Without resetting the PLL, the phase relationship between the clocks is
unpredictable. Fix this by resetting the PLL in si5351_clkout_prepare().
References:
[1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf
Figure 12 ("I2C Programming Procedure")
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
---
drivers/clk/clk-si5351.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index aba2895..9c4cc5d 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -903,13 +903,42 @@ static int _si5351_clkout_set_disable_state(
return 0;
}
+void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
+{
+ u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
+
+ switch (val & SI5351_CLK_INPUT_MASK) {
+ case SI5351_CLK_INPUT_XTAL:
+ case SI5351_CLK_INPUT_CLKIN:
+ return; /* pll not used, no need to reset */
+ }
+
+ si5351_reg_write(drvdata, SI5351_PLL_RESET,
+ val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
+ SI5351_PLL_RESET_A);
+
+ dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
+ __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
+ (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
+}
+
static int si5351_clkout_prepare(struct clk_hw *hw)
{
struct si5351_hw_data *hwdata =
container_of(hw, struct si5351_hw_data, hw);
+ struct si5351_platform_data *pdata =
+ hwdata->drvdata->client->dev.platform_data;
si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
SI5351_CLK_POWERDOWN, 0);
+
+ /*
+ * Do a pll soft reset on the parent pll -- needed to get a
+ * deterministic phase relationship between the output clocks.
+ */
+ if (pdata->clkout[hwdata->num].pll_reset)
+ _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
+
si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
(1 << hwdata->num), 0);
return 0;
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread