Re: [PATCH v11 6/6] clk: qcom: Add APCS clock controller support

[Stephen Boyd <sboyd@codeaurora.org>]

On 12/05, Georgi Djakov wrote:
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include "clk-regmap.h"
> +#include "clk-regmap-mux-div.h"
> +
> +enum {
> +	P_GPLL0,
> +	P_A53PLL,
> +};

This is always 0, 1.

> +
> +static const struct parent_map gpll0_a53cc_map[] = {
> +	{ P_GPLL0, 4 },
> +	{ P_A53PLL, 5 },

And then this is not really doing much. So I wonder why we really
even need a parent_map? More like we need a map from parent_names
to mux number. We don't need to map some random enum into another
number space like we do for RCGs. I think we may have the same
problem with another qcom clk patch (see commit df964016490b in
clk-next). We really don't need the rcg version of parent_map in
either case, more like we just need a u8 *table (or u32
whatever), and then we're done. I'm going to make that change now
because otherwise we get into a mess with the parent_map stuff in
the other branch. I'll go clean up that too so we don't move
parent_map around.

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