Re: [PATCH 0/3] clk: ti: add CLK_SET_RATE_PARENT support for clkctrl

[Tony Lindgren <tony@atomide.com>]

* Tero Kristo <t-kristo@ti.com> [180227 06:35]:
> On 27/02/18 00:05, Tony Lindgren wrote:
> > Hi,
> > 
> > * Tero Kristo <t-kristo@ti.com> [180226 15:11]:
> > > This patch adds clock rate propagation support for clkctrl clocks. This
> > > is needed on am33xx beaglebone black device at least, otherwise the
> > > display does not work. Similar problem appears to be present on am43xx
> > > but haven't heard of any reports of such so far, maybe Jyri can confirm
> > > this?
> > 
> > I think I was also hitting this with the system timers with ti-sysc
> > where set_parent() would fail unless the dts has the following for
> > timers:
> > 
> > clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
> > 
> > So bit 24 instead of 0.
> > 
> > Hmm so should we have all the timers use bit 0 in the dtsi?
> > Or default to bit 24 for all of them?
> 
> Who is going to control the clkctrl clock for the timers if you just control
> the opt clock? Also, ain't the bit 24 the clksel mux setting? Tweaking that
> would seem wrong...

Yeah OK.

> If you were facing problems with setting the clock source, we could maybe
> just apply the CLK_SET_RATE_PARENT globally to all clkctrl clocks (modify
> the patch #1 in this series to always set the flag, instead of clecking
> against the CLKF_xyz flag.) Any thoughts?

Sounds good to me if that keeps omap_dm_timer_init_one() working
for clk_set_parent() for configuring timer via dts :)

I think there's a reserved range for the parent clocks that is
different from the opt clocks in the clkctrl registers so it
can be maybe checked that way?

Regards,

Tony