Linux clock framework development
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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<mturquette@baylibre.com>, <sboyd@codeaurora.org>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<devicetree@vger.kernel.org>, <lgirdwood@gmail.com>,
	<broonie@kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 07/11] dt-bindings: tegra: Update DFLL binding for PWM regulator
Date: Mon, 12 Mar 2018 11:10:36 +0200	[thread overview]
Message-ID: <20180312091036.GR6190@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <c747bc00-8c04-c297-e945-784e45655421@nvidia.com>

On Thu, Mar 08, 2018 at 11:21:40PM +0000, Jon Hunter wrote:
> 
> On 06/02/18 16:34, Peter De Schrijver wrote:
> > Add new properties to configure the DFLL PWM regulator support. Also
> > add an example and make the I2C clock only required when I2C support is
> > used.
> > 
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> >  .../bindings/clock/nvidia,tegra124-dfll.txt        | 76 +++++++++++++++++++++-
> >  1 file changed, 74 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> > index dff236f..a4903f7 100644
> > --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> > +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> > @@ -23,7 +23,8 @@ Required properties:
> >  - clock-names: Must include the following entries:
> >    - soc: Clock source for the DFLL control logic.
> >    - ref: The closed loop reference clock
> > -  - i2c: Clock source for the integrated I2C master.
> > +  - i2c: Clock source for the integrated I2C master (only required when
> > +	 using I2C mode).
> >  - resets: Must contain an entry for each entry in reset-names.
> >    See ../reset/reset.txt for details.
> >  - reset-names: Must include the following entries:
> > @@ -45,10 +46,28 @@ Required properties for the control loop parameters:
> >  Optional properties for the control loop parameters:
> >  - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
> >  
> > +Optional properties for mode selection:
> > +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
> > +
> 
> Do we need this property? Seems that we should be able to detect if it
> is I2C or PWM based upon the other properties.
> 

I guess we could look for nvidia,pwm-period and switch to PWM mode if this is
found, but I think it's more clear to have explicit property.

Peter.

  reply	other threads:[~2018-03-12  9:10 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-06 16:34 [PATCH v3 00/11] Tegra210 DFLL implementation Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 01/11] regulator: core: add API to get voltage constraints Peter De Schrijver
2018-02-06 16:35   ` Mark Brown
2018-02-07  8:47     ` Peter De Schrijver
2018-02-07 10:43       ` Mark Brown
2018-02-07 12:37         ` Peter De Schrijver
2018-02-07 14:18           ` Mark Brown
2018-02-07 14:32             ` Peter De Schrijver
2018-02-07 15:01               ` Mark Brown
2018-02-07 15:20                 ` Peter De Schrijver
2018-02-07 15:37                   ` Mark Brown
2018-02-08 10:04                     ` Laxman Dewangan
2018-02-08 14:58                       ` Mark Brown
2018-02-06 16:34 ` [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework Peter De Schrijver
2018-03-08 22:26   ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs Peter De Schrijver
2018-03-08 22:15   ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Peter De Schrijver
2018-03-08 22:28   ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 05/11] clk: tegra: prepare dfll driver for PWM regulator Peter De Schrijver
2018-03-08 22:50   ` Jon Hunter
2018-03-12  9:14     ` Peter De Schrijver
2018-03-12 11:08       ` Jon Hunter
2018-03-13  9:03         ` Peter De Schrijver
2018-03-13 10:07           ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 06/11] clk: tegra: dfll: support PWM regulator control Peter De Schrijver
2018-03-08 23:15   ` Jon Hunter
2018-03-09  8:12     ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 07/11] dt-bindings: tegra: Update DFLL binding for PWM regulator Peter De Schrijver
2018-02-09 23:19   ` Rob Herring
2018-03-08 23:21   ` Jon Hunter
2018-03-12  9:10     ` Peter De Schrijver [this message]
2018-02-06 16:34 ` [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210 Peter De Schrijver
2018-03-08 23:22   ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 Peter De Schrijver
2018-03-08 23:25   ` Jon Hunter
2018-03-09  8:14     ` Peter De Schrijver
2018-03-12 10:14       ` Jon Hunter
2018-03-13  9:28         ` Peter De Schrijver
2018-03-09  9:11   ` Viresh Kumar
2018-03-12 12:15   ` Jon Hunter
2018-03-13  9:51     ` Peter De Schrijver
2018-03-13 10:20       ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 10/11] arm64: dts: tegra: Add Tegra210 DFLL definition Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 11/11] arm64: dts: nvidia: Tegra210 CPU clock definition Peter De Schrijver

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