Re: [PATCH v3 6/8] clk: tegra20: Turn EMC clock gate into divider

Stephen Boyd
2018-07-09T00:00:17Z

Quoting Dmitry Osipenko (2018-06-17 07:55:37)
> Kernel should never gate the EMC clock as it causes immediate lockup, so
> removing clk-gate functionality doesn't affect anything. Turning EMC clk
> gate into divider allows to implement glitch-less EMC scaling, avoiding
> reparenting to a backup clock.
> =

> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---

Who's supposed to apply this? Me? Thierry? The "To:" line is not
useful when every maintainer is there.

> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegr=
a20.c
> index cc857d4d4a86..2bd35418716a 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -799,6 +798,31 @@ static struct tegra_periph_init_data tegra_periph_no=
div_clk_list[] =3D {
> TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2=
, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
> };
> =

> +static void __init tegra20_emc_clk_init(void)
> +{
> + struct clk *clk;
> +
> + clk =3D clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
> + ARRAY_SIZE(mux_pllmcp_clkm),
> + CLK_SET_RATE_NO_REPARENT,
> + clk_base + CLK_SOURCE_EMC,
> + 30, 2, 0, &emc_lock);
> +
> + clk =3D tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOU=
RCE_EMC,
> + &emc_lock);
> + clks[TEGRA20_CLK_MC] =3D clk;
> +
> + /*
> + * Note that 'emc_mux' source and 'emc' rate shouldn't be changed=
at
> + * the same time due to a HW bug, this won't happen because we're
> + * defining 'emc_mux' and 'emc' as a distinct clocks.

s/ a//