From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com ([192.55.52.88]:19289 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726413AbeHCE6b (ORCPT ); Fri, 3 Aug 2018 00:58:31 -0400 From: Songjun Wu To: hua.ma@linux.intel.com, yixin.zhu@linux.intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com Cc: linux-mips@linux-mips.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, Songjun Wu , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Jiri Slaby Subject: [PATCH v2 13/18] serial: intel: Replace clk_enable/clk_disable with clk generic API Date: Fri, 3 Aug 2018 11:02:32 +0800 Message-Id: <20180803030237.3366-14-songjun.wu@linux.intel.com> In-Reply-To: <20180803030237.3366-1-songjun.wu@linux.intel.com> References: <20180803030237.3366-1-songjun.wu@linux.intel.com> Sender: linux-clk-owner@vger.kernel.org List-ID: The clk driver has introduced new clock APIs that replace the existing clk_enable and clk_disable. -clk_enable() APIs is replaced with clk_prepare_enable(). -clk_disable() API is replaced with clk_disable_unprepare(). Signed-off-by: Songjun Wu --- Changes in v2: None drivers/tty/serial/lantiq.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 28086d52e980..36479d66fb7c 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -309,7 +309,7 @@ lqasc_startup(struct uart_port *port) int retval; if (!IS_ERR(ltq_port->clk)) - clk_enable(ltq_port->clk); + clk_prepare_enable(ltq_port->clk); port->uartclk = clk_get_rate(ltq_port->freqclk); asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), @@ -377,7 +377,7 @@ lqasc_shutdown(struct uart_port *port) asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, port->membase + LTQ_ASC_TXFCON); if (!IS_ERR(ltq_port->clk)) - clk_disable(ltq_port->clk); + clk_disable_unprepare(ltq_port->clk); } static void @@ -631,7 +631,7 @@ lqasc_console_setup(struct console *co, char *options) port = <q_port->port; if (!IS_ERR(ltq_port->clk)) - clk_enable(ltq_port->clk); + clk_prepare_enable(ltq_port->clk); port->uartclk = clk_get_rate(ltq_port->freqclk); -- 2.11.0