From: Jordan Crouse <jcrouse@codeaurora.org>
To: sboyd@kernel.org, mturquette@baylibre.com
Cc: andy.gross@linaro.org, david.brown@linaro.org,
rnayak@codeaurora.org, okukatla@codeaurora.org,
tdas@codeaurora.org, linux-arm-msm@vger.kernel.orgi,
linux-soc@vger.kernel.org, linux-clk@vger.kernel.org,
robdclark@gmail.com, freedreno@lists.freedesktop.org
Subject: [PATCH 1/4] drm/msm/a6xx: Remove unwanted regulator code
Date: Mon, 19 Nov 2018 16:47:03 -0700 [thread overview]
Message-ID: <20181119234706.5821-2-jcrouse@codeaurora.org> (raw)
In-Reply-To: <20181119234706.5821-1-jcrouse@codeaurora.org>
The GMU code currently has some misguided code to try to work around
a hardware quirk that requires the power domains on the GPU be
collapsed in a certain order. Upcoming patches will do this the
right way so get rid of the unused and unwanted regulator
code.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ----
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 --
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 546599a7ab05..51493f409358 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -646,9 +646,6 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu)
gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
(val & 1), 100, 1000);
- /* Force off the GX GSDC */
- regulator_force_disable(gmu->gx);
-
/* Disable the resources */
clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
pm_runtime_put_sync(gmu->dev);
@@ -1173,7 +1170,6 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
pm_runtime_enable(gmu->dev);
- gmu->gx = devm_regulator_get(gmu->dev, "vdd");
/* Get the list of clocks */
ret = a6xx_gmu_clocks_probe(gmu);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 35f765afae45..a871cae2fc5e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -52,8 +52,6 @@ struct a6xx_gmu {
int hfi_irq;
int gmu_irq;
- struct regulator *gx;
-
struct iommu_domain *domain;
u64 uncached_iova_base;
--
2.18.0
next prev parent reply other threads:[~2018-11-19 23:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-19 23:47 [RFC 0/4] msm: clk: Define a special power domain for SDM845 GX Jordan Crouse
2018-11-19 23:47 ` Jordan Crouse [this message]
2018-11-21 7:55 ` [PATCH 1/4] drm/msm/a6xx: Remove unwanted regulator code Stephen Boyd
2018-11-19 23:47 ` [PATCH 2/4] clk: qcom: gdsc: Don't override existing gdsc pd functions Jordan Crouse
2018-11-20 4:30 ` Rajendra Nayak
2018-11-19 23:47 ` [PATCH 3/4] clk: qcom: Add a dummy enable function for GX gdsc Jordan Crouse
2018-11-19 23:47 ` [PATCH 4/4] drm/msm/gpu: Attach to the GPU GX power domain Jordan Crouse
2018-11-21 7:54 ` Stephen Boyd
2018-11-21 15:00 ` Jordan Crouse
2018-11-21 19:24 ` Stephen Boyd
2018-11-21 8:00 ` [RFC 0/4] msm: clk: Define a special power domain for SDM845 GX Stephen Boyd
2018-11-21 15:04 ` Jordan Crouse
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