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[217.229.16.64]) by smtp.gmail.com with ESMTPSA id 24sm1647115eds.97.2018.11.28.01.24.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Nov 2018 01:24:04 -0800 (PST) Date: Wed, 28 Nov 2018 10:24:04 +0100 From: Thierry Reding To: Peter De Schrijver Cc: Marcel Ziswiler , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Marcel Ziswiler , Stephen Boyd , Prashant Gaikwad , Jonathan Hunter , Michael Turquette , linux-clk@vger.kernel.org Subject: Re: [PATCH v1 2/3] clk: tegra: ignore unused vfir clock shared with uartb Message-ID: <20181128092404.GF17419@ulmo> References: <20181101015230.27310-1-marcel@ziswiler.com> <20181101015230.27310-3-marcel@ziswiler.com> <20181101084152.GS7636@tbergstrom-lnx.Nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="924gEkU1VlJlwnwX" Content-Disposition: inline In-Reply-To: <20181101084152.GS7636@tbergstrom-lnx.Nvidia.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org --924gEkU1VlJlwnwX Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Nov 01, 2018 at 10:41:52AM +0200, Peter De Schrijver wrote: > On Thu, Nov 01, 2018 at 02:52:29AM +0100, Marcel Ziswiler wrote: > > From: Marcel Ziswiler > >=20 > > As UARTB and VFIR share their clock enable bit it is rather unwise for > > the kernel to turn off the VFIR one should that be unused (and > > potentially vice versa but so far there anyway is no VFIR driver). > >=20 > > Without this patch trying to use UARTB with the regular 8250 driver > > will freeze as soon as ttyS1 is accessed after boot. Luckily, using the > > high-speed Tegra serial driver won't exhibit the issue as clocks are > > dynamically enabled/disabled on every access. > >=20 > > This has been reproduced both on Apalis T30 as well as Apalis TK1 but > > may be an issue on all Tegra UARTB's which share the clock enable with > > VFIR. > >=20 >=20 > Ah.. the correct fix for this is to initialize the enable_refcnt based on= the > hw state. This is done in 9619dba8325fce098bbc9ee2911d1b0150fec0c9 for > periph gate clocks, but obviously also applies to normal periph clocks. Hi Marcel, were you going to send a new version with the alternative fix as suggested by Peter? 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