From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CEA7C04EB8 for ; Tue, 4 Dec 2018 09:27:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0344420851 for ; Tue, 4 Dec 2018 09:27:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Jd+uUEYv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0344420851 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-clk-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725981AbeLDJ1C (ORCPT ); Tue, 4 Dec 2018 04:27:02 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4069 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeLDJ1C (ORCPT ); Tue, 4 Dec 2018 04:27:02 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Dec 2018 01:27:02 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Dec 2018 01:27:00 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Dec 2018 01:27:00 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:27:00 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 4 Dec 2018 09:26:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 4 Dec 2018 09:26:59 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 04 Dec 2018 01:26:59 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Viresh Kumar , Subject: [PATCH 11/19] cpufreq: tegra124: do not handle the CPU rail Date: Tue, 4 Dec 2018 17:25:40 +0800 Message-ID: <20181204092548.3038-12-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543915622; bh=keK1cFRn89M3cmuIffiAPACzFEXeNYnLBLsdkkMVf14=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Jd+uUEYvcxJq3OU88H3tbNTlHTaVCEMqDNSjyQujoU4J09+7ZmWys6r9nmvO1ankt 9ftaPNTEfkFlGxe30ofdCPM69HLkOv9Sd26hDDUz6ch6R3NAN7VMMMdeBz86xEO9px 7wfygFfoNDmRl8oMk/+o2eNpWISvZjrp1Z4kTbX1xbPCali+GRLXFJkQpf3JrLTgP8 9y3nt1nO3BfRscqExQ2ImTRVADyLuRLY8dVSpJVsOtAYmKZsDhXYRggWIWYEWcnvoM Ph+Pyl4pso+jH6LvCAu59YRh++mERFAY9zVmxdMoIifoek+Jtz4DGz3XkT/IlKGTo1 p+SE1/TCDyNzg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Tegra124 cpufreq driver has no information to handle the Vdd-CPU rail. So the driver shouldn't handle for the CPU clock switching from DFLL to other PLL clocks. It was designed to work on DFLL clock only, which handle the frequency/voltage scaling in the background. This patch removes the driver dependency of the CPU rail. Cc: Viresh Kumar Cc: linux-pm@vger.kernel.org Signed-off-by: Joseph Lo --- drivers/cpufreq/Kconfig.arm | 2 +- drivers/cpufreq/tegra124-cpufreq.c | 26 ++------------------------ 2 files changed, 3 insertions(+), 25 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 4e1131ef85ae..a609f8820c47 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -262,7 +262,7 @@ config ARM_TEGRA20_CPUFREQ =20 config ARM_TEGRA124_CPUFREQ tristate "Tegra124 CPUFreq support" - depends on ARCH_TEGRA && CPUFREQ_DT && REGULATOR + depends on ARCH_TEGRA && CPUFREQ_DT default y help This adds the CPUFreq driver support for Tegra124 SOCs. diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-= cpufreq.c index 43530254201a..448d00763d00 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -22,11 +22,9 @@ #include #include #include -#include #include =20 struct tegra124_cpufreq_priv { - struct regulator *vdd_cpu_reg; struct clk *cpu_clk; struct clk *pllp_clk; struct clk *pllx_clk; @@ -60,14 +58,6 @@ static int tegra124_cpu_switch_to_dfll(struct tegra124_c= pufreq_priv *priv) return ret; } =20 -static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv= ) -{ - clk_set_parent(priv->cpu_clk, priv->pllp_clk); - clk_disable_unprepare(priv->dfll_clk); - regulator_sync_voltage(priv->vdd_cpu_reg); - clk_set_parent(priv->cpu_clk, priv->pllx_clk); -} - static int tegra124_cpufreq_probe(struct platform_device *pdev) { struct tegra124_cpufreq_priv *priv; @@ -88,16 +78,10 @@ static int tegra124_cpufreq_probe(struct platform_devic= e *pdev) if (!np) return -ENODEV; =20 - priv->vdd_cpu_reg =3D regulator_get(cpu_dev, "vdd-cpu"); - if (IS_ERR(priv->vdd_cpu_reg)) { - ret =3D PTR_ERR(priv->vdd_cpu_reg); - goto out_put_np; - } - priv->cpu_clk =3D of_clk_get_by_name(np, "cpu_g"); if (IS_ERR(priv->cpu_clk)) { ret =3D PTR_ERR(priv->cpu_clk); - goto out_put_vdd_cpu_reg; + goto out_put_np; } =20 priv->dfll_clk =3D of_clk_get_by_name(np, "dfll"); @@ -129,15 +113,13 @@ static int tegra124_cpufreq_probe(struct platform_dev= ice *pdev) platform_device_register_full(&cpufreq_dt_devinfo); if (IS_ERR(priv->cpufreq_dt_pdev)) { ret =3D PTR_ERR(priv->cpufreq_dt_pdev); - goto out_switch_to_pllx; + goto out_put_pllp_clk; } =20 platform_set_drvdata(pdev, priv); =20 return 0; =20 -out_switch_to_pllx: - tegra124_cpu_switch_to_pllx(priv); out_put_pllp_clk: clk_put(priv->pllp_clk); out_put_pllx_clk: @@ -146,8 +128,6 @@ static int tegra124_cpufreq_probe(struct platform_devic= e *pdev) clk_put(priv->dfll_clk); out_put_cpu_clk: clk_put(priv->cpu_clk); -out_put_vdd_cpu_reg: - regulator_put(priv->vdd_cpu_reg); out_put_np: of_node_put(np); =20 @@ -159,13 +139,11 @@ static int tegra124_cpufreq_remove(struct platform_de= vice *pdev) struct tegra124_cpufreq_priv *priv =3D platform_get_drvdata(pdev); =20 platform_device_unregister(priv->cpufreq_dt_pdev); - tegra124_cpu_switch_to_pllx(priv); =20 clk_put(priv->pllp_clk); clk_put(priv->pllx_clk); clk_put(priv->dfll_clk); clk_put(priv->cpu_clk); - regulator_put(priv->vdd_cpu_reg); =20 return 0; } --=20 2.19.2