From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3015AC65BAE for ; Thu, 13 Dec 2018 09:35:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A531C20811 for ; Thu, 13 Dec 2018 09:35:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="gsJK/a58" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A531C20811 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-clk-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728075AbeLMJfd (ORCPT ); Thu, 13 Dec 2018 04:35:33 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8199 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727890AbeLMJfc (ORCPT ); Thu, 13 Dec 2018 04:35:32 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:35:27 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:35:32 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:35:32 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:35:31 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:35:31 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 13 Dec 2018 01:35:31 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH V2 18/21] arm64: dts: tegra210-p2371-2180: enable DFLL clock Date: Thu, 13 Dec 2018 17:34:35 +0800 Message-ID: <20181213093438.29621-19-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693727; bh=0f1C/zHS4phrkAxTk4eJ0AWcd0x+IDXCjE0ZaS045U8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=gsJK/a58F2RseeopFry3FPdXakOynCGGcAvTX+dwYUbws6Yiyp4b4O70gPLbGYFs6 AFrjF9ibmyRQykTXI8jTb7ddYRvyLpkLEsbhnU1f/JAkHva8RglRTCZRhZBMu9glR3 VcvQ1lPybqf0bzZxvBVo87RaAY2u5BSQf0b3XKRLnyelO5F14uUX9fokCSHZlklq6u ZtRMkO4ImXr0/O/VNVaV0jLQlRvvpvSh3SRX/FKOeD1rAPguO79XESL5XLeBJv1dcq 4gkpHPXkVzRRo3HiuJkXUTJoN230kUo1TetSfnXMgVMxpWVBQgY6ntT66F+avmyN5s 3wnoFOYYQtecA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Enable DFLL clock for Jetson TX1 platform. Signed-off-by: Joseph Lo --- *V2: - remove non exist DT bindings - update the PWM DT bindings accordingly --- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm6= 4/boot/dts/nvidia/tegra210-p2371-2180.dts index 37e3c46e753f..99c016bfc601 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -78,4 +78,25 @@ }; }; }; + + clock@70110000 { + status =3D "okay"; + + nvidia,cf =3D <6>; + nvidia,ci =3D <0>; + nvidia,cg =3D <2>; + nvidia,droop-ctrl =3D <0x00000f00>; + nvidia,force-mode =3D <1>; + nvidia,sample-rate =3D <25000>; + + nvidia,pwm-min-microvolts =3D <708000>; + nvidia,pwm-period =3D <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts =3D <1000000>; + nvidia,pwm-voltage-step-microvolts =3D <19200>; + + pinctrl-names =3D "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 =3D <&dvfs_pwm_active_state>; + pinctrl-1 =3D <&dvfs_pwm_inactive_state>; + }; }; --=20 2.19.2