From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF306C43387 for ; Tue, 18 Dec 2018 09:13:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D1E5217D8 for ; Tue, 18 Dec 2018 09:13:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="G0bjM3Kq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726486AbeLRJNV (ORCPT ); Tue, 18 Dec 2018 04:13:21 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14279 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726406AbeLRJNV (ORCPT ); Tue, 18 Dec 2018 04:13:21 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Dec 2018 01:13:15 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 18 Dec 2018 01:13:20 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 18 Dec 2018 01:13:20 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 18 Dec 2018 09:13:20 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 18 Dec 2018 09:13:19 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 18 Dec 2018 09:13:19 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 18 Dec 2018 01:13:19 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH V3 15/20] arm64: dts: tegra210: add CPU clocks Date: Tue, 18 Dec 2018 17:12:27 +0800 Message-ID: <20181218091232.23532-16-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218091232.23532-1-josephl@nvidia.com> References: <20181218091232.23532-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545124395; bh=smyj6lzWqIAN8RuiPcPX1YUGaRLDbgN8/syxKRAV3uE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=G0bjM3Kq3a+xoKihc2uFWUQxOqY86gUHk+6v0LdwVc28m5F0vyCHSO78ST5Lv+8/7 Y+/3DYQSHCGQoWgVLdtKrDDNaDgtTHQmys4qd9dx0S6caNU9BT9IZqAcnxopFTqMAP ot7xwdB5gqxWUkx+9lHUFhIsvfzGBCXMcsuPiAOxKDQlsiiVkCtRzoRaS9XQKjTCp+ Rf8djwMXetSqqnN07tkmZbnJboyCGkh+eNzutLpTOoXjRlxBhdrMfkIhCpVymz0APk 7gae9ZR+E+kcZpUDGsrSsE6XKS01NHGN8qUtmXbsmIiMBTv3FkjPBQwEbi9e26AIXV dJmxaMfp61HzA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add CPU clocks for Tegra210. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V3: - no change *V2: - add ack tag --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts= /nvidia/tegra210.dtsi index a6db62157442..e2baf52fe1af 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1304,6 +1304,12 @@ device_type =3D "cpu"; compatible =3D "arm,cortex-a57"; reg =3D <0>; + clocks =3D <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, + <&dfll>; + clock-names =3D "cpu_g", "pll_x", "pll_p", "dfll"; + clock-latency =3D <300000>; }; =20 cpu@1 { --=20 2.20.1