From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DBA7C43444 for ; Fri, 4 Jan 2019 03:07:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F22D820449 for ; Fri, 4 Jan 2019 03:07:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="NhO9R+LW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727015AbfADDHd (ORCPT ); Thu, 3 Jan 2019 22:07:33 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12323 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726073AbfADDHd (ORCPT ); Thu, 3 Jan 2019 22:07:33 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 03 Jan 2019 19:07:12 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 03 Jan 2019 19:07:32 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 03 Jan 2019 19:07:32 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 4 Jan 2019 03:07:32 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 4 Jan 2019 03:07:32 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 03 Jan 2019 19:07:31 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH V4 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Date: Fri, 4 Jan 2019 11:06:52 +0800 Message-ID: <20190104030702.8684-11-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190104030702.8684-1-josephl@nvidia.com> References: <20190104030702.8684-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546571232; bh=c3Rx9IYRqpKkOQ6LVZlYipMaTVOxAGNMmnr2Yoh4g9U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=NhO9R+LWbEJxXIiv72ZJdNZ+VpTxKgdwWxoKNyNBXM+4vLVedhTIxFt4SBB0MSusi s8KLj4A4alrXwkZDKdp++h37gqWoDLckZg12/5+CGiDrmnA2giZjYGCDXpsExPHB59 ybzwKq7xC6o9BKblrkzWQbseRtBo2eNiwUJt+tA2tMeRziiREMOP66ZRB+GfL813QE gGUKcsDdDTNGValwSmXqqPz4vOmVCAu4DqcTjv/s9FOs4G2FZxTKY7PeeAdm1M82NQ vbLP4iXhXKzzoCZvDCgdtldgAHKxc116XWLTfBA5A80UOX/w8aLBxQmUnwZKGE0LSZ FWaV+27XjvS/g== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peter De Schrijver Tegra210 has a DFLL as well and can share the majority of the code with the Tegra124 implementation. So build the same code for both platforms. Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V4: - remove parenthesis in Kconfig of DFLL driver *V3: - no change *V2: - add ack tag --- drivers/clk/tegra/Kconfig | 5 +++++ drivers/clk/tegra/Makefile | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig index 7ddacae5d0b1..1adcccfa7829 100644 --- a/drivers/clk/tegra/Kconfig +++ b/drivers/clk/tegra/Kconfig @@ -5,3 +5,8 @@ config TEGRA_CLK_EMC config CLK_TEGRA_BPMP def_bool y depends on TEGRA_BPMP + +config TEGRA_CLK_DFLL + depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC + select PM_OPP + def_bool y diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 6507acc843c7..4812e45c2214 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) +=3D clk-tegra20.= o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) +=3D clk-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) +=3D clk-tegra114.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) +=3D clk-tegra124.o -obj-$(CONFIG_ARCH_TEGRA_124_SOC) +=3D clk-tegra124-dfll-fcpu.o +obj-$(CONFIG_TEGRA_CLK_DFLL) +=3D clk-tegra124-dfll-fcpu.o obj-$(CONFIG_ARCH_TEGRA_132_SOC) +=3D clk-tegra124.o obj-y +=3D cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D clk-tegra210.o --=20 2.20.1