From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 574D1C10F00 for ; Wed, 20 Feb 2019 02:54:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 22F022146F for ; Wed, 20 Feb 2019 02:54:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730377AbfBTCy2 (ORCPT ); Tue, 19 Feb 2019 21:54:28 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:62030 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730321AbfBTCy1 (ORCPT ); Tue, 19 Feb 2019 21:54:27 -0500 X-UUID: f042b27c668a494697ebb7d4618a4d8a-20190220 X-UUID: f042b27c668a494697ebb7d4618a4d8a-20190220 Received: from mtkcas34.mediatek.inc [(172.27.4.250)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1080677928; Wed, 20 Feb 2019 10:54:20 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 20 Feb 2019 10:54:18 +0800 Received: from mszsdaap41.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 20 Feb 2019 10:54:17 +0800 From: wangyan wang To: Michael Turquette , Stephen Boyd , CK Hu CC: wangyan wang , Matthias Brugger , Philipp Zabel , David Airlie , Daniel Vetter , chunhui dai , Colin Ian King , Sean Wang , Ryder Lee , , , , , , Subject: [PATCH V5 6/8] clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel Date: Wed, 20 Feb 2019 10:53:55 +0800 Message-ID: <20190220025357.7354-7-wangyan.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20190220025357.7354-1-wangyan.wang@mediatek.com> References: <20190220025357.7354-1-wangyan.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: chunhui dai The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF. Signed-off-by: chunhui dai Signed-off-by: wangyan wang --- drivers/clk/mediatek/clk-mt2701.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index ab6ab07f53e6..905a2316f6a7 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = { 0x0080, 8, 2, 15), MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23), - MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, - 0x0080, 24, 2, 31), + MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, + 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST), MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7), -- 2.14.1