From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8838DC4360F for ; Tue, 5 Mar 2019 05:07:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 67D7620675 for ; Tue, 5 Mar 2019 05:07:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726329AbfCEFGv (ORCPT ); Tue, 5 Mar 2019 00:06:51 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:32013 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726085AbfCEFGH (ORCPT ); Tue, 5 Mar 2019 00:06:07 -0500 X-UUID: 4a601cbace9f40328335c2da1bd4b5e4-20190305 X-UUID: 4a601cbace9f40328335c2da1bd4b5e4-20190305 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1061337124; Tue, 05 Mar 2019 13:05:56 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 13:05:55 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 13:05:55 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , , Weiyi Lu Subject: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Date: Tue, 5 Mar 2019 13:05:46 +0800 Message-ID: <20190305050546.23431-11-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190305050546.23431-1-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 104CB3A5F888D3C353C3151EF2B2F2C9E12C8E12A49C6AB5DD017CD1D5FD3D3E2000:8 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: James Liao Some modules may need to change its clock rate before turn on it. So changing PLL's rate when it is off should be allowed. This patch removes PLL enabled check before set rate, so that PLLs can set new frequency even if they are off. On MT8173 for example, ARMPLL's enable bit can be controlled by other HW. That means ARMPLL may be turned on even if we (CPU / SW) set ARMPLL's enable bit as 0. In this case, SW may want and can still change ARMPLL's rate by changing its pcw and postdiv settings. But without this patch, new pcw setting will not be applied because its enable bit is 0. Signed-off-by: James Liao Acked-by: Michael Turquette Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-pll.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 65cee1d6c400..8d556fc99fed 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) { u32 chg, val; - int pll_en; - - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; /* disable tuner */ __mtk_pll_tuner_disable(pll); @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, pll->data->pcw_shift); val |= pcw << pll->data->pcw_shift; writel(val, pll->pcw_addr); - - chg = readl(pll->pcw_chg_addr); - - if (pll_en) - chg |= PCW_CHG_MASK; - + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; writel(chg, pll->pcw_chg_addr); if (pll->tuner_addr) writel(val + 1, pll->tuner_addr); @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, /* restore tuner_en */ __mtk_pll_tuner_enable(pll); - if (pll_en) - udelay(20); + udelay(20); } /* -- 2.18.0