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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id c9sm11004164pfn.3.2019.06.16.21.36.45 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 16 Jun 2019 21:36:45 -0700 (PDT) Date: Sun, 16 Jun 2019 21:37:34 -0700 From: Bjorn Andersson To: Vinod Koul Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, Andy Gross , David Brown , Michael Turquette , linux-clk@vger.kernel.org Subject: Re: [PATCH v2 1/5] clk: qcom: clk-alpha-pll: Remove unnecessary cast Message-ID: <20190617043734.GH750@tuxbook-pro> References: <20190612091722.9377-1-vkoul@kernel.org> <20190612091722.9377-2-vkoul@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190612091722.9377-2-vkoul@kernel.org> User-Agent: Mutt/1.11.4 (2019-03-13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Wed 12 Jun 02:17 PDT 2019, Vinod Koul wrote: > We have couple of instances in the driver with unnecessary > u64 casts, drop them. > > Signed-off-by: Vinod Koul > --- > drivers/clk/qcom/clk-alpha-pll.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index 0ced4a5a9a17..b48707693ffd 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -832,7 +832,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, > int div; > > /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ > - div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; > + div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; Afaict DIV_ROUND_UP_ULL() will first add "parent_rate" and "rate" and then stash this in a unsigned long long and do the division. So what happens if parent_rate + rate > 32 bits on a 32-bit target? (Shouldn't there be a cast of (ll) in the macro to ULL?) Regards, Bjorn > > return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), > PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, > @@ -1094,7 +1094,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, > return -EINVAL; > } > > - div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); > + div = DIV_ROUND_UP_ULL(parent_rate, rate); > for (i = 0; i < pll->num_post_div; i++) { > if (pll->post_div_table[i].div == div) { > val = pll->post_div_table[i].val; > -- > 2.20.1 >