From: Stephen Boyd <sboyd@kernel.org>
To: Dinh Nguyen <dinguyen@kernel.org>, linux-clk@vger.kernel.org
Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org,
mturquette@baylibre.com, stable@vger.kernel.org
Subject: Re: [PATCH] clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Date: Wed, 14 Aug 2019 09:23:23 -0700 [thread overview]
Message-ID: <20190814162324.BF27020665@mail.kernel.org> (raw)
In-Reply-To: <20190814153014.12962-1-dinguyen@kernel.org>
Quoting Dinh Nguyen (2019-08-14 08:30:14)
> Checking bypass_reg is incorrect for calculating the cnt_clk rates.
> Instead we should be checking that there is a proper hardware register
> that holds the clock divider.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
Applied to clk-fixes
prev parent reply other threads:[~2019-08-14 16:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-14 15:30 [PATCH] clk: socfpga: stratix10: fix rate caclulationg for cnt_clks Dinh Nguyen
2019-08-14 16:23 ` Stephen Boyd [this message]
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