From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Icenowy Zheng <icenowy@aosc.io>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Sasha Levin <sashal@kernel.org>,
linux-clk@vger.kernel.org
Subject: [PATCH AUTOSEL 5.3 29/87] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
Date: Tue, 24 Sep 2019 12:40:45 -0400 [thread overview]
Message-ID: <20190924164144.25591-29-sashal@kernel.org> (raw)
In-Reply-To: <20190924164144.25591-1-sashal@kernel.org>
From: Icenowy Zheng <icenowy@aosc.io>
[ Upstream commit 720099603d1f62e37b789366d7e89824b009ca28 ]
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.
Fix this issue.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 9b3939fc7faa6..5ca4d34b4094f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -502,6 +502,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
+ [CLK_MMC2] = &mmc2_clk.common.hw,
+ [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
+ [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
--
2.20.1
next prev parent reply other threads:[~2019-09-24 17:02 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190924164144.25591-1-sashal@kernel.org>
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 23/87] clk: imx8mq: Mark AHB clock as critical Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 27/87] clk: qoriq: Fix -Wunused-const-variable Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 28/87] clk: ingenic/jz4740: Fix "pll half" divider not read/written properly Sasha Levin
2019-09-24 16:40 ` Sasha Levin [this message]
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 36/87] clk: actions: Don't reference clk_init_data after registration Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 37/87] clk: sirf: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 38/87] clk: meson: axg-audio: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 39/87] clk: sprd: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 40/87] clk: zx296718: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 41/87] clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 57/87] clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 58/87] clk: renesas: cpg-mssr: " Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 70/87] clk: qcom: gcc-sdm845: Use floor ops for sdcc clks Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 76/87] clk: at91: select parent if main oscillator or bypass is enabled Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 77/87] clk: imx: pll14xx: avoid glitch when set rate Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 78/87] clk: imx: clk-pll14xx: unbypass PLL by default Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 79/87] clk: Make clk_bulk_get_all() return a valid "id" Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 82/87] clk: sprd: add missing kfree Sasha Levin
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