From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Chunyan Zhang <chunyan.zhang@unisoc.com>,
Chunyan Zhang <zhang.lyra@gmail.com>,
Stephen Boyd <sboyd@kernel.org>, Sasha Levin <sashal@kernel.org>,
linux-clk@vger.kernel.org
Subject: [PATCH AUTOSEL 5.3 82/87] clk: sprd: add missing kfree
Date: Tue, 24 Sep 2019 12:41:38 -0400 [thread overview]
Message-ID: <20190924164144.25591-82-sashal@kernel.org> (raw)
In-Reply-To: <20190924164144.25591-1-sashal@kernel.org>
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
[ Upstream commit 5e75ea9c67433a065b0e8595ad3c91c7c0ca0d2d ]
The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.
Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/clk/sprd/pll.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
index 36b4402bf09e3..640270f51aa56 100644
--- a/drivers/clk/sprd/pll.c
+++ b/drivers/clk/sprd/pll.c
@@ -136,6 +136,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
k2 + refin * nint * CLK_PLL_1M;
}
+ kfree(cfg);
return rate;
}
@@ -222,6 +223,7 @@ static int _sprd_pll_set_rate(const struct sprd_pll *pll,
if (!ret)
udelay(pll->udelay);
+ kfree(cfg);
return ret;
}
--
2.20.1
prev parent reply other threads:[~2019-09-24 16:45 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190924164144.25591-1-sashal@kernel.org>
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 23/87] clk: imx8mq: Mark AHB clock as critical Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 27/87] clk: qoriq: Fix -Wunused-const-variable Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 28/87] clk: ingenic/jz4740: Fix "pll half" divider not read/written properly Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 29/87] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 36/87] clk: actions: Don't reference clk_init_data after registration Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 37/87] clk: sirf: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 38/87] clk: meson: axg-audio: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 39/87] clk: sprd: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 40/87] clk: zx296718: " Sasha Levin
2019-09-24 16:40 ` [PATCH AUTOSEL 5.3 41/87] clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 57/87] clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 58/87] clk: renesas: cpg-mssr: " Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 70/87] clk: qcom: gcc-sdm845: Use floor ops for sdcc clks Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 76/87] clk: at91: select parent if main oscillator or bypass is enabled Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 77/87] clk: imx: pll14xx: avoid glitch when set rate Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 78/87] clk: imx: clk-pll14xx: unbypass PLL by default Sasha Levin
2019-09-24 16:41 ` [PATCH AUTOSEL 5.3 79/87] clk: Make clk_bulk_get_all() return a valid "id" Sasha Levin
2019-09-24 16:41 ` Sasha Levin [this message]
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