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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 3ftyLwbBo/4E9niyrfVEN44Zq4Ek32Nc7uXy1rf4JBeiOZLscDJmGoKSYHUdenAc2ZIoiS29x7wSwRIR1Gzj0bND5s93gWrbu5xWGozw2v0pIexkcM/AYtv2UkH7eegZ5X44urPmHz3OVzd/Ltue2YYY4nTUMb5bB0nVAmjhq70udvHFoEx3/8wZ0XERec1EE3mZ8PqR+TM1LfTyHed/w2Rdj9ZVMrMKWvIPO+jzcoA4Wq05MPh4KsCMrQL33FYoMTzc5pQpT62zbql0fOm+yduaPPsW1VaWbACK+qacU7KYSQDZ9T0ji9PB57l6bW8VjFmixsPWMVORm8dEpl+v1mQ1cE7kCBXh8kbPqd6UCzJ3gW2r1xXpjlRq2pPJ16igE72PjHlmykhnZ+s2iQlJkj6xTtCdAX6QrYOLKgd0yg4= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b50d3614-cc04-4487-6512-08d7511e3263 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Oct 2019 03:17:23.5456 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WF9dOQn2o+cZRmkXv2gmNKcyFiAZL4L7kltw577Lv8V2DKECrOuxku1hKbCXO7ec2qoEe6UYRbVTH7Q4+AdPWA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5414 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The mipi pll clock comes from the MIPI PHY PLL output, so it should not be a fixed clock. MIPI PHY PLL is in the MIPI DSI space, and it is used as the bit clock for transferring the pixel data out and its output clock is configured according to the display mode. So it should be used only for MIPI DSI and not be exported out for other usages. Signed-off-by: Fancy Fang --- ChangeLog v2->v3: * Keep 'IMX7ULP_CLK_MIPI_PLL' macro definition. ChangeLog v1->v2: * Keep other clock indexes unchanged as Shawn suggested. Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 - drivers/clk/imx/clk-imx7ulp.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Do= cumentation/devicetree/bindings/clock/imx7ulp-clock.txt index a4f8cd478f92..93d89adb7afe 100644 --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt @@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 { <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 2022d9bead91..459b120b71d5 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -28,7 +28,7 @@ static const char * const scs_sels[] =3D { "dummy", "sos= c", "sirc", "firc", "dumm static const char * const ddr_sels[] =3D { "apll_pfd_sel", "upll", }; static const char * const nic_sels[] =3D { "firc", "ddr_clk", }; static const char * const periph_plat_sels[] =3D { "dummy", "nic1_bus_clk"= , "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; -static const char * const periph_bus_sels[] =3D { "dummy", "sosc_bus_clk",= "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk"= , }; +static const char * const periph_bus_sels[] =3D { "dummy", "sosc_bus_clk",= "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk= ", }; static const char * const arm_sels[] =3D { "divcore", "dummy", "dummy", "= hsrun_divcore", }; =20 /* used by sosc/sirc/firc/ddr/spll/apll dividers */ @@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_no= de *np) clks[IMX7ULP_CLK_SOSC] =3D imx_obtain_fixed_clk_hw(np, "sosc"); clks[IMX7ULP_CLK_SIRC] =3D imx_obtain_fixed_clk_hw(np, "sirc"); clks[IMX7ULP_CLK_FIRC] =3D imx_obtain_fixed_clk_hw(np, "firc"); - clks[IMX7ULP_CLK_MIPI_PLL] =3D imx_obtain_fixed_clk_hw(np, "mpll"); clks[IMX7ULP_CLK_UPLL] =3D imx_obtain_fixed_clk_hw(np, "upll"); =20 /* SCG1 */ --=20 2.17.1