Linux clock framework development
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From: Lubomir Rintel <lkundrak@v3.sk>
To: Sasha Levin <sashal@kernel.org>
Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org,
	Stephen Boyd <sboyd@kernel.org>, Olof Johansson <olof@lixom.net>,
	linux-clk@vger.kernel.org
Subject: Re: [PATCH AUTOSEL 5.4 028/107] clk: mmp2: Fix the order of timer mux parents
Date: Fri, 24 Jan 2020 22:08:33 +0100	[thread overview]
Message-ID: <20200124210833.GA244505@furthur.local> (raw)
In-Reply-To: <20200124141817.28793-28-sashal@kernel.org>

On Fri, Jan 24, 2020 at 09:16:58AM -0500, Sasha Levin wrote:
> From: Lubomir Rintel <lkundrak@v3.sk>
> 
> [ Upstream commit 8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad ]
> 
> Determined empirically, no documentation is available.
> 
> The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
> thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
> what is going on, ended up just dividing the rate as of
> commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'

Hi,

this has to go together with this one (in other stable trees too):

  commit 0bd0f30bbf060891f58866a46083a9931f71787c
  Author: Lubomir Rintel <lkundrak@v3.sk>
  Date:   Wed Dec 18 20:04:53 2019 +0100
  
      ARM: mmp: do not divide the clock rate
      
      This was done because the clock driver returned the wrong rate, which is
      fixed in "clk: mmp2: Fix the order of timer mux parents" patch.

It removes a workaround for the same issue from before it was
understood what is going on. If it stays, the clock will run twice as
fast.

Thanks
Lubo

> 
> Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Olof Johansson <olof@lixom.net>
> Signed-off-by: Sasha Levin <sashal@kernel.org>
> ---
>  drivers/clk/mmp/clk-of-mmp2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
> index a60a1be937ad6..b4a95cbbda989 100644
> --- a/drivers/clk/mmp/clk-of-mmp2.c
> +++ b/drivers/clk/mmp/clk-of-mmp2.c
> @@ -134,7 +134,7 @@ static DEFINE_SPINLOCK(ssp3_lock);
>  static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
>  
>  static DEFINE_SPINLOCK(timer_lock);
> -static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"};
> +static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
>  
>  static DEFINE_SPINLOCK(reset_lock);
>  
> -- 
> 2.20.1
> 

      reply	other threads:[~2020-01-24 21:08 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200124141817.28793-1-sashal@kernel.org>
2020-01-24 14:16 ` [PATCH AUTOSEL 5.4 002/107] clk: sunxi-ng: v3s: Fix incorrect number of hw_clks Sasha Levin
2020-01-24 14:16 ` [PATCH AUTOSEL 5.4 022/107] clk: Don't try to enable critical clocks if prepare failed Sasha Levin
2020-01-24 14:16 ` [PATCH AUTOSEL 5.4 023/107] clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock Sasha Levin
2020-01-24 14:16 ` [PATCH AUTOSEL 5.4 024/107] clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order Sasha Levin
2020-01-24 14:16 ` [PATCH AUTOSEL 5.4 027/107] clk: qcom: gcc-sdm845: Add missing flag to votable GDSCs Sasha Levin
2020-01-24 14:16 ` [PATCH AUTOSEL 5.4 028/107] clk: mmp2: Fix the order of timer mux parents Sasha Levin
2020-01-24 21:08   ` Lubomir Rintel [this message]

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