* [PATCH v12 10/11] clk: pwm: Use 64-bit division function [not found] <cover.1586414867.git.gurus@codeaurora.org> @ 2020-04-09 6:52 ` Guru Das Srinagesh 2020-04-10 19:15 ` Guru Das Srinagesh 0 siblings, 1 reply; 2+ messages in thread From: Guru Das Srinagesh @ 2020-04-09 6:52 UTC (permalink / raw) To: linux-pwm Cc: Thierry Reding, Uwe Kleine-König, Subbaraman Narayanamurthy, David Collins, linux-kernel, Guru Das Srinagesh, Michael Turquette, Stephen Boyd, linux-clk Since the PWM framework is switching struct pwm_args.period's datatype to u64, prepare for this transition by using div64_u64 to handle a 64-bit divisor. Also ensure that divide-by-zero (with fixed_rate as denominator) does not happen with an explicit check with probe failure as a consequence. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org> --- drivers/clk/clk-pwm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c index 87fe0b0e..86f2e2d 100644 --- a/drivers/clk/clk-pwm.c +++ b/drivers/clk/clk-pwm.c @@ -89,7 +89,12 @@ static int clk_pwm_probe(struct platform_device *pdev) } if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate)) - clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period; + clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period); + + if (!clk_pwm->fixed_rate) { + dev_err(&pdev->dev, "fixed_rate cannot be zero\n"); + return -EINVAL; + } if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate && pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v12 10/11] clk: pwm: Use 64-bit division function 2020-04-09 6:52 ` [PATCH v12 10/11] clk: pwm: Use 64-bit division function Guru Das Srinagesh @ 2020-04-10 19:15 ` Guru Das Srinagesh 0 siblings, 0 replies; 2+ messages in thread From: Guru Das Srinagesh @ 2020-04-10 19:15 UTC (permalink / raw) To: linux-pwm Cc: Thierry Reding, Uwe Kleine-König, Subbaraman Narayanamurthy, David Collins, linux-kernel, Michael Turquette, Stephen Boyd, linux-clk, David Laight, Arnd Bergmann + Arnd, David On Wed, Apr 08, 2020 at 11:52:39PM -0700, Guru Das Srinagesh wrote: > Since the PWM framework is switching struct pwm_args.period's datatype > to u64, prepare for this transition by using div64_u64 to handle a > 64-bit divisor. > > Also ensure that divide-by-zero (with fixed_rate as denominator) does > not happen with an explicit check with probe failure as a consequence. > > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: linux-clk@vger.kernel.org > > Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org> > --- > drivers/clk/clk-pwm.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c > index 87fe0b0e..86f2e2d 100644 > --- a/drivers/clk/clk-pwm.c > +++ b/drivers/clk/clk-pwm.c > @@ -89,7 +89,12 @@ static int clk_pwm_probe(struct platform_device *pdev) > } > > if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate)) > - clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period; > + clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period); > + > + if (!clk_pwm->fixed_rate) { > + dev_err(&pdev->dev, "fixed_rate cannot be zero\n"); > + return -EINVAL; > + } > > if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate && > pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) { > -- Hello Arnd, David: Sorry, missed cc-ing you both to this patch while sending it out. Could you please review it when you get a chance to? Thank you. Guru Das. ^ permalink raw reply [flat|nested] 2+ messages in thread
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2020-04-09 6:52 ` [PATCH v12 10/11] clk: pwm: Use 64-bit division function Guru Das Srinagesh
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