Re: [PATCH 2/4] clk: qcom: Add SDX55 GCC support

Stephen Boyd
2020-11-13T07:58:24Z

Quoting Manivannan Sadhasivam (2020-11-05 00:51:48)
> On Wed, Nov 04, 2020 at 06:23:37PM -0800, Stephen Boyd wrote:
> > > diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c
> > > new file mode 100644
> > > index 000000000000..75831c829202
> > > --- /dev/null
> > > +++ b/drivers/clk/qcom/gcc-sdx55.c
> > > @@ -0,0 +1,1667 @@
> > > +
>
> [...]
>
> > > +static const struct clk_div_table post_div_table_lucid_even[] = {
> > > + { 0x0, 1 },
> > > + { 0x1, 2 },
> > > + { 0x3, 4 },
> > > + { 0x7, 8 },
> > > + { }
> > > +};
> >
> > I think this table is common to all lucid plls? Maybe we can push it
> > into the clk_ops somehow and stop duplicating it here?
> >
>
> Are you referring to lucid plls in this driver? Because, this table is
> not common for other SoCs. And I don't think having this way introduces
> any overhead, so I'd prefer keeping it as it is.
>

Yes all lucid type PLLs probably have the same divider table.

>
> > > +/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
> > > +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
> > > + .halt_reg = 0x4010,
> > > + .halt_check = BRANCH_HALT_VOTED,
> > > + .clkr = {
> > > + .enable_reg = 0x6d008,
> > > + .enable_mask = BIT(0),
> > > + .hw.init = &(struct clk_init_data){
> > > + .name = "gcc_sys_noc_cpuss_ahb_clk",
> > > + .parent_hws = (const struct clk_hw *[]){
> > > + &gcc_cpuss_ahb_clk_src.clkr.hw },
> > > + .num_parents = 1,
> > > + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
> >
> > These CLK_IS_CRITICAL clks can't be set once at driver probe time and
> > forgotten about? It would be nice to not allocate memory for things that
> > never matter.
> >
>
> Makes sense! But are we moving into the direction of deprecating the use
> of CLK_IS_CRITICAL?

No? Just judiciously using it.