From: Robert Hancock <robert.hancock@calian.com>
To: mturquette@baylibre.com, sboyd@kernel.org
Cc: mike.looijmans@topic.nl, robh+dt@kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
Robert Hancock <robert.hancock@calian.com>
Subject: [PATCH v3 5/9] clk: si5341: Update initialization magic
Date: Thu, 25 Mar 2021 13:26:39 -0600 [thread overview]
Message-ID: <20210325192643.2190069-6-robert.hancock@calian.com> (raw)
In-Reply-To: <20210325192643.2190069-1-robert.hancock@calian.com>
Update the default register settings to include the VCO_RESET_CALCODE
settings (set by the SiLabs ClockBuilder software but not described in
the datasheet). Also update part of the initialization sequence to match
ClockBuilder and the datasheet.
Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
drivers/clk/clk-si5341.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index da40b90c2aa8..eb22f4fdbc6b 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -350,6 +350,8 @@ static const struct si5341_reg_default si5341_reg_defaults[] = {
{ 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
{ 0x0A02, 0x00 }, /* Not in datasheet */
{ 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
+ { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
+ { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
};
/* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
@@ -1104,7 +1106,7 @@ static const struct si5341_reg_default si5341_preamble[] = {
{ 0x0B25, 0x00 },
{ 0x0502, 0x01 },
{ 0x0505, 0x03 },
- { 0x0957, 0x1F },
+ { 0x0957, 0x17 },
{ 0x0B4E, 0x1A },
};
--
2.27.0
next prev parent reply other threads:[~2021-03-25 19:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 19:26 [PATCH v3 0/9] Si5341 driver updates Robert Hancock
2021-03-25 19:26 ` [PATCH v3 1/9] dt-bindings: clock: clk-si5341: Add new attributes Robert Hancock
2021-03-27 15:27 ` Rob Herring
2021-06-28 3:02 ` Stephen Boyd
2021-03-25 19:26 ` [PATCH v3 2/9] clk: si5341: Wait for DEVICE_READY on startup Robert Hancock
2021-06-28 3:02 ` Stephen Boyd
2021-03-25 19:26 ` [PATCH v3 3/9] clk: si5341: Avoid divide errors due to bogus register contents Robert Hancock
2021-06-28 3:02 ` Stephen Boyd
2021-03-25 19:26 ` [PATCH v3 4/9] clk: si5341: Check for input clock presence and PLL lock on startup Robert Hancock
2021-06-28 3:02 ` Stephen Boyd
2021-03-25 19:26 ` Robert Hancock [this message]
2021-06-28 3:02 ` [PATCH v3 5/9] clk: si5341: Update initialization magic Stephen Boyd
2021-03-25 19:26 ` [PATCH v3 6/9] clk: si5341: Allow different output VDD_SEL values Robert Hancock
2021-06-28 3:02 ` Stephen Boyd
2021-03-25 19:26 ` [PATCH v3 7/9] clk: si5341: Add silabs,xaxb-ext-clk property Robert Hancock
2021-06-28 3:02 ` Stephen Boyd
2021-03-25 19:26 ` [PATCH v3 8/9] clk: si5341: Add silabs,iovdd-33 property Robert Hancock
2021-06-28 3:02 ` Stephen Boyd
2021-03-25 19:26 ` [PATCH v3 9/9] clk: si5341: Add sysfs properties to allow checking/resetting device faults Robert Hancock
2021-06-28 3:03 ` Stephen Boyd
2021-04-07 16:50 ` [PATCH v3 0/9] Si5341 driver updates Robert Hancock
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