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From: Stephen Boyd <sboyd@kernel.org>
To: Loic Poulain <loic.poulain@linaro.org>
Cc: agross@kernel.org, bjorn.andersson@linaro.org,
	robh+dt@kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	shawn.guo@linaro.org
Subject: Re: [PATCH v2 1/2] clk: qcom: Add display clock controller driver for QCM2290
Date: Thu, 16 Dec 2021 17:37:01 -0800	[thread overview]
Message-ID: <20211217013703.63A46C36AE0@smtp.kernel.org> (raw)
In-Reply-To: <CAMZdPi9eAFaExcTTgOt6TFE37EA-bb9xSy3nq9=nKYd5kqwmfQ@mail.gmail.com>

Quoting Loic Poulain (2021-12-16 11:21:51)
> Hi Stephen,
> 
> 
> On Thu, 16 Dec 2021 at 04:49, Stephen Boyd <sboyd@kernel.org> wrote:
> >
> > Quoting Loic Poulain (2021-12-09 06:09:10)
> > > diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> > > new file mode 100644
> > > index 00000000..8aa5d31
> > > --- /dev/null
> > > +++ b/drivers/clk/qcom/dispcc-qcm2290.c
> > > @@ -0,0 +1,602 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> > > + * Copyright (c) 2021, Linaro Ltd.
> > > + */
> > > +
> [...]
> > > +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
> > > +       .cmd_rcgr = 0x205c,
> > > +       .mnd_width = 8,
> > > +       .hid_width = 5,
> > > +       .parent_map = disp_cc_parent_map_4,
> > > +       .clkr.hw.init = &(struct clk_init_data){
> > > +               .name = "disp_cc_mdss_pclk0_clk_src",
> > > +               .parent_data = disp_cc_parent_data_4,
> > > +               .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
> > > +               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
> >
> > These last two flags are needed for what?
> 
> NOCACHE is probably useless with mainline.

Ok then please remove it.

> 
> I've added OPS_PARENT_ENABLE because AFAIU changing clock rate can
> lead to parent switch, and parent switch can only be done if parent
> clocks are enabled for rcg2 clocks. Otherwise the update fails and we
> get the following:
>     disp_cc_mdss_pclk0_clk_src: rcg didn't update its configuration.
>     WARNING: CPU: 2 PID: 77 at drivers/clk/qcom/clk-rcg2.c:122
> update_config+0xe0/0xf0
> 
> I'm a bit surprised other similar dispcc drivers don't use the same
> flags though.

That's quite odd. We migrate the prepare and enable count to the new
parent in the core framework so is the rcg on, but doesn't look like it
is on to the core and set_rate is being called?

  reply	other threads:[~2021-12-17  1:37 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-09 14:09 [PATCH v2 1/2] clk: qcom: Add display clock controller driver for QCM2290 Loic Poulain
2021-12-09 14:09 ` [PATCH v2 2/2] dt-bindings: clock: Add qualcomm QCM2290 DISPCC bindings Loic Poulain
2021-12-15  3:41   ` Bjorn Andersson
2021-12-15 18:13   ` Rob Herring
2021-12-15  3:39 ` [PATCH v2 1/2] clk: qcom: Add display clock controller driver for QCM2290 Bjorn Andersson
2021-12-16  3:49 ` Stephen Boyd
2021-12-16 19:21   ` Loic Poulain
2021-12-17  1:37     ` Stephen Boyd [this message]
2021-12-17  1:58       ` Dmitry Baryshkov
2021-12-17 16:16     ` Steev Klimaszewski
2021-12-17 16:54       ` Loic Poulain

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