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From: Stephen Boyd <sboyd@kernel.org>
To: Adam Wujek <dev_public@wujek.eu>,
	Michael Turquette <mturquette@baylibre.com>,
	Robert Hancock <robert.hancock@calian.com>
Cc: Adam Wujek <dev_public@wujek.eu>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: si5341: fix reported clk_rate when output divider is 2
Date: Thu, 13 Jan 2022 13:23:10 -0800	[thread overview]
Message-ID: <20220113212312.19D85C36AE3@smtp.kernel.org> (raw)
In-Reply-To: <20211203141125.2447520-1-dev_public@wujek.eu>

+Robert

Please review

Quoting Adam Wujek (2021-12-03 06:12:07)
> SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether
> a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2
> is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set,
> SI5341_OUT_R_REG is set 0).
> Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was
> interpreted as output is disabled.
> 
> Signed-off-by: Adam Wujek <dev_public@wujek.eu>
> ---
>  drivers/clk/clk-si5341.c | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
> index b7641abe6747..15b1c90cafe5 100644
> --- a/drivers/clk/clk-si5341.c
> +++ b/drivers/clk/clk-si5341.c
> @@ -798,6 +798,15 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
>         u32 r_divider;
>         u8 r[3];
> 
> +       err = regmap_read(output->data->regmap,
> +                       SI5341_OUT_CONFIG(output), &val);
> +       if (err < 0)
> +               return err;
> +
> +       /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
> +       if (val & SI5341_OUT_CFG_RDIV_FORCE2)
> +               return parent_rate / 2;
> +
>         err = regmap_bulk_read(output->data->regmap,
>                         SI5341_OUT_R_REG(output), r, 3);
>         if (err < 0)
> @@ -814,13 +823,6 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
>         r_divider += 1;
>         r_divider <<= 1;
> 
> -       err = regmap_read(output->data->regmap,
> -                       SI5341_OUT_CONFIG(output), &val);
> -       if (err < 0)
> -               return err;
> -
> -       if (val & SI5341_OUT_CFG_RDIV_FORCE2)
> -               r_divider = 2;
> 
>         return parent_rate / r_divider;
>  }

  reply	other threads:[~2022-01-13 21:23 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-03 14:12 [PATCH] clk: si5341: fix reported clk_rate when output divider is 2 Adam Wujek
2022-01-13 21:23 ` Stephen Boyd [this message]
2022-01-13 22:29   ` Robert Hancock
2022-01-25  0:51 ` Stephen Boyd

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