Re: [PATCH 2/2] clk: rs9: Add Renesas 9-series PCIe clock generator driver

Stephen Boyd
2022-02-19T03:05:26Z

Quoting Marek Vasut (2022-02-18 17:11:04)
> On 2/18/22 23:15, Stephen Boyd wrote:
> >>
> >>>> + if (!parent_clk)
> >>>> + return dev_err_probe(&client->dev, -EINVAL,
> >>>> + "Missing XTal input clock\n");
> >>>> +
> >>>> + rs9->regmap = devm_regmap_init_i2c(client, &rs9_regmap_config);
> >>>> + if (IS_ERR(rs9->regmap))
> >>>> + return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap),
> >>>> + "Failed to allocate register map\n");
> >>>> +
> >>>> + /* Register clock */
> >>>> + for (i = 0; i < rs9->chip_info->num_clks; i++) {
> >>>> + name[3]++;
> >>>> + hw = clk_hw_register_fixed_factor(&client->dev, name,
> >>>> + parent_clk, 0, 4, 1);
> >
> > To do that it looks like maybe we'll need to export
> > __clk_hw_register_fixed_factor() and introduces some sort of
> > clk_hw_register_fixed_factor_parent_data() API.
>
> Setting parent_clk to NULL should be enough.
>

Perfect, but also weird. I worry that's a bug that snuck in. Probably a
good idea to not rely on that.