RE: [PATCH 5/8] dma: dw: Avoid partial transfers

Phil Edworthy
2022-02-21T08:14:54Z

Hi Andy,

I wrote the patch a few years ago, but didn't get the time to upstream it.

I am not aware of a HW integration bug on the RZ/N1 device but can't rule it out. I am struggling to see what kind of HW issue this could be as, iirc, word accesses work fine when the size of the transfer is a multiple of the MEM width.

I found the issue when testing DMA with the UART transferring different amounts of data.

> > + if (sconfig->dst_addr_width && sconfig->dst_addr_width <
> data_width)
> > + data_width = sconfig->dst_addr_width;
>
> But here no check that you do it for explicitly peripheral to memory, so
> this
> will affect memory to peripheral transfers as well.
No, this should be ok as this change is within:
case DMA_DEV_TO_MEM:

BR
Phil

> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: 20 February 2022 10:50
> To: Miquel Raynal <miquel.raynal@bootlin.com>
> Cc: Viresh Kumar <vireshk@kernel.org>; Vinod Koul <vkoul@kernel.org>;
> Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>; Michael Turquette <mturquette@baylibre.com>;
> Stephen Boyd <sboyd@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> devicetree@vger.kernel.org; dmaengine@vger.kernel.org; linux-renesas-
> soc@vger.kernel.org; linux-clk@vger.kernel.org; Thomas Petazzoni
> <thomas.petazzoni@bootlin.com>; Milan Stevanovic
> <milan.stevanovic@se.com>; Jimmy Lalande <jimmy.lalande@se.com>; Laetitia
> MARIOTTINI <laetitia.mariottini@se.com>; Phil Edworthy
> <phil.edworthy@renesas.com>
> Subject: Re: [PATCH 5/8] dma: dw: Avoid partial transfers
>
> On Fri, Feb 18, 2022 at 07:12:23PM +0100, Miquel Raynal wrote:
> > From: Phil Edworthy <phil.edworthy@renesas.com>
> >
> > Pausing a partial transfer only causes data to be written to mem that is
> > a multiple of the memory width setting.
> >
> > However, when a DMA client driver finishes DMA early, e.g. due to UART
> > char timeout interrupt, all data read from the DEV must be written to
> MEM.
> >
> > Therefore, allow the slave to limit the memory width to ensure all data
> > read from the DEV is written to MEM when DMA is paused.
>
> Is this a fix?
> What happens to the data if you don't do this?
> As far as I understood the Synopsys DesignWare specification the DMA
> controller
> is capable of flushing FIFO in that case on byte-by-byte basis. Do you
> have an
> HW integration bug?
>
> TL;DR: tell us more about this.
>
> ...
>
> > + if (sconfig->dst_addr_width && sconfig->dst_addr_width <
> data_width)
> > + data_width = sconfig->dst_addr_width;
>
> But here no check that you do it for explicitly peripheral to memory, so
> this
> will affect memory to peripheral transfers as well.
>
>
> --
> With Best Regards,
> Andy Shevchenko
>