From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01271C433EF for ; Thu, 10 Mar 2022 23:45:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238905AbiCJXqU (ORCPT ); Thu, 10 Mar 2022 18:46:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232493AbiCJXqT (ORCPT ); Thu, 10 Mar 2022 18:46:19 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20F66C12E3; Thu, 10 Mar 2022 15:45:13 -0800 (PST) X-UUID: 8eb3cdbf9b844ea48027def2f2d42723-20220311 X-UUID: 8eb3cdbf9b844ea48027def2f2d42723-20220311 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2135811672; Fri, 11 Mar 2022 07:45:10 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 11 Mar 2022 07:45:09 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Mar 2022 07:45:09 +0800 From: Miles Chen To: CC: , , , , , , , , , , Subject: Re: [PATCH v2 01/15] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock Date: Fri, 11 Mar 2022 07:45:09 +0800 Message-ID: <20220310234509.32636-1-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220221015258.913-2-chun-jie.chen@mediatek.com> References: <20220221015258.913-2-chun-jie.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Chun-Jie, > [PATCH v2 01/15] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock s/Mediatek/MediaTek/ > This patch adds the new binding documentation for system clock > and functional clock on Mediatek MT8186. s/Mediatek/MediaTek/ > > Signed-off-by: Chun-Jie Chen > --- > .../arm/mediatek/mediatek,mt8186-clock.yaml | 56 +++ > .../mediatek/mediatek,mt8186-sys-clock.yaml | 54 +++ > include/dt-bindings/clock/mt8186-clk.h | 445 ++++++++++++++++++ > 3 files changed, 555 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml > create mode 100644 include/dt-bindings/clock/mt8186-clk.h > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml > new file mode 100644 > index 000000000000..373e8a100da3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Mediatek Functional Clock Controller for MT8186 s/Mediatek/MediaTek/ > + > +maintainers: > + - Chun-Jie Chen > + > +description: > + The clock architecture in Mediatek like below s/Mediatek/MediaTek/ > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The devices provide clock gate control in different IP blocks. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8186-imp_iic_wrap > + - mediatek,mt8186-mfgsys > + - mediatek,mt8186-wpesys > + - mediatek,mt8186-imgsys1 > + - mediatek,mt8186-imgsys2 > + - mediatek,mt8186-vdecsys > + - mediatek,mt8186-vencsys > + - mediatek,mt8186-camsys > + - mediatek,mt8186-camsys_rawa > + - mediatek,mt8186-camsys_rawb > + - mediatek,mt8186-mdpsys > + - mediatek,mt8186-ipesys > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + imp_iic_wrap: clock-controller@11017000 { > + compatible = "mediatek,mt8186-imp_iic_wrap"; > + reg = <0x11017000 0x1000>; > + #clock-cells = <1>; > + }; > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml > new file mode 100644 > index 000000000000..4c071dd66b76 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Mediatek System Clock Controller for MT8186 > s/Mediatek/MediaTek/ > + > +maintainers: > + - Chun-Jie Chen > + > +description: > + The clock architecture in Mediatek like below s/Mediatek/MediaTek/ Thanks, Miles