[PATCH v10 8/9] ARM: dts: r9a06g032: Add the two DMA nodes

Miquel Raynal
2022-04-12T19:41:06Z

Describe the two DMA controllers available on this SoC.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r9a06g032.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 636a6ab31c58..839580ec21ee 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -200,6 +200,36 @@ nand_controller: nand-controller@40102000 {
status = "disabled";
};

+ dma0: dma-controller@40104000 {
+ compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
+ reg = <0x40104000 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "hclk";
+ clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
+ dma-channels = <8>;
+ dma-requests = <16>;
+ dma-masters = <1>;
+ #dma-cells = <3>;
+ block_size = <0xfff>;
+ data_width = <3>;
+ status = "disabled";
+ };
+
+ dma1: dma-controller@40105000 {
+ compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
+ reg = <0x40105000 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "hclk";
+ clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
+ dma-channels = <8>;
+ dma-requests = <16>;
+ dma-masters = <1>;
+ #dma-cells = <3>;
+ block_size = <0xfff>;
+ data_width = <3>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
--
2.27.0