Re: [PATCH 1/7] clk: mediatek: reset: Correct the logic of setting register

Rex-BC Chen
2022-04-19T06:38:54Z

On Tue, 2022-04-19 at 13:48 +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Mon, Apr 18, 2022 at 9:22 PM Rex-BC Chen <rex-bc.chen@mediatek.com
> > wrote:
> >
>
> The subject could be written as "Fix written reset bit offset" to
> make it
> more specific.

Hello ChenYu,

I will update the topic in next version.
Thanks for your suggestion.

BRs,
Rex

>
> > Original assert/deassert bit is BIT(0), but it's more resonable to
> > modify
> > them to BIT(id % 32) which is based on id.
> >
> > This patch will not influence any previous driver because the reset
> > is
> > only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is
> > 0.
> >
> > Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>
> Otherwise,
>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>