Re: [PATCH v4 2/5] clk: qcom: regmap: add pipe clk implementation

Johan Hovold
2022-05-09T10:30:02Z

On Fri, May 06, 2022 at 03:40:18PM +0300, Dmitry Baryshkov wrote:
> On 06/05/2022 15:31, Johan Hovold wrote:

> > The only thing that comes to mind that wouldn't be possible is to
> > set the mux state using an assigned clock parent in devicetree to make
> > sure that XO is always selected before toggling the GDSC at probe.
> >
> > But since that doesn't seem to work anyway when the boot firmware has
> > set things up (e.g. causes a modem here to reset) that would probably
> > need to be handled in the GDSC driver anyway (i.e. make sure the source
> > is XO before enabling the GDSC but only when it was actually disabled).
> >
> > Taking that one step further would be to implement all this in the GDSC
> > driver from the start so that the PHY PLL is always muxed in while the
> > power domain is enabled (and only then)...
>
> I think, if we move this to the gdsc driver, we'd loose the part of the
> clock tree.

Not necessarily, if the GDSC is modeled as a consumer of the mux.

> If you don't mind, I'll wait for your Tested-by and will post the rename
> patchset afterwards.

I've tested the series and it works as expected. I'll retest the final
version before giving my Tested-by.

Johan