Re: [PATCH v11 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling

Bjorn Helgaas
2022-07-07T20:04:10Z

[+cc Selvam, Baruch, Robert, Krishna, Krzysztof (other contributors to
qcom)]

On Thu, Jul 07, 2022 at 10:40:23AM -0500, Bjorn Helgaas wrote:
> On Thu, Jul 07, 2022 at 05:03:48PM +0300, Dmitry Baryshkov wrote:
> > On 16/06/2022 21:21, Bjorn Helgaas wrote:
> > > On Wed, Jun 08, 2022 at 01:52:33PM +0300, Dmitry Baryshkov wrote:
> > > > PCIe pipe clk (and some other clocks) must be parked to the "safe"
> > > > source (bi_tcxo) when corresponding GDSC is turned off and on again.
> > > > Currently this is handcoded in the PCIe driver by reparenting the
> > > > gcc_pipe_N_clk_src clock.

> > > > Dmitry Baryshkov (5):
> > > > clk: qcom: regmap: add PHY clock source implementation
> > > > clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe
> > > > clocks
> > > > clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe
> > > > clocks
> > > > PCI: qcom: Remove unnecessary pipe_clk handling
> > > > PCI: qcom: Drop manual pipe_clk_src handling

> > > I applied this to pci/ctrl/qcom for v5.20, thanks!
> > >
> > > Clock folks (Bjorn A, Andy, Michael, Stephen), I assume you're OK with
> > > these being merged via the PCI tree. Let me know if you prefer
> > > anything different.
> >
> > I noticed that this patchset is not a part of linux-next. Is it still
> > pending to be merged in 5.20?
>
> It's still pending. I currently have three separate qcom-related
> branches that need to be reconciled before I put them in -next.

The first three patches are on an immutable branch from the clock
tree:

74e4190cdebe ("clk: qcom: regmap: add PHY clock source implementation")
7ee9d2e8b9c9 ("clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks")
553d12b20c10 ("clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks")

I added the rest on top of that:

cbd27d5c2ccf ("PCI: qcom: Move IPQ8074 DBI register accesses after phy_power_on()")
633c1fa00ab9 ("PCI: qcom: Move all DBI register accesses after phy_power_on()")
e835e9859548 ("dt-bindings: PCI: qcom: Fix description typo")
55e8a13ec92f ("PCI: qcom: Remove unnecessary pipe_clk handling")
1690864ec3c8 ("PCI: dwc: tegra: move GEN3_RELATED DBI register to common header")
39e0a12b484b ("PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*")
44d07e984b93 ("PCI: qcom: Add IPQ60xx support")

and pushed it to a pci/ctrl/qcom-pending branch so you can check it
out. It's "pending" for now because I really want an ack and some
testing for 633c1fa00ab9 ("PCI: qcom: Move all DBI register accesses
after phy_power_on()").

There's a LOT of stuff going on in qcom-land this cycle, and it's
coming from a lot of different people. We can deal with that, but it
does complicate things and slow them down. I think it would be easier
and speed things up if we could figure out how to coordinate things on
the qcom side.

Bjorn