Re: [PATCH 12/12] clk: mmp: pxa168: control shared SDH bits with separate clock

Stephen Boyd
2022-09-30T20:45:50Z

Quoting Doug Brown (2022-06-12 12:29:37)
> The PXA168 has a peculiar setup with the AXI clock enable control for
> the SDHC controllers. The bits in the SDH0 register control the AXI
> clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2
> register control both SDH2 and SDH3. This is modeled with two new
> parentless clocks that control the shared bits.
>
> Previously, SDH0 had to be enabled in order for SDH1 to be used, and
> when SDH1 was enabled, unused bits in the SDH1 register were being
> controlled. This fixes those issues. A future commit will add support
> for these new shared clocks to be enabled by the PXA168 SDHC driver.
>
> Signed-off-by: Doug Brown <doug@schmorgal.com>
> ---

Applied to clk-next