Re: [PATCH 3/4] arm64: dts: qcom: add power domain for clk controller

[Bjorn Andersson <andersson@kernel.org>]

On Fri, Aug 05, 2022 at 03:49:34PM +0800, Jun Nie wrote:
> Add RPM power domain for clk controller so that clock controller can
> use it for dynamic voltage frequency scaling.
> 
> Also replace the RPM power domain value with defninition.
> 
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 05472510e29d..fdb32b3a23e8 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -312,22 +312,22 @@ rpmpd_opp_table: opp-table {
>  						compatible = "operating-points-v2";
>  
>  						rpmpd_opp_ret: opp1 {
> -							opp-level = <1>;
> +							opp-level = <RPM_SMD_CORNER_RETENTION>;
>  						};
>  						rpmpd_opp_svs_krait: opp2 {
> -							opp-level = <2>;
> +							opp-level = <RPM_SMD_CORNER_SVS_KRAIT>;
>  						};
>  						rpmpd_opp_svs_soc: opp3 {
> -							opp-level = <3>;
> +							opp-level = <RPM_SMD_CORNER_SVS_SOC>;
>  						};
>  						rpmpd_opp_nom: opp4 {
> -							opp-level = <4>;
> +							opp-level = <RPM_SMD_CORNER_NORMAL>;
>  						};
>  						rpmpd_opp_turbo: opp5 {
> -							opp-level = <5>;
> +							opp-level = <RPM_SMD_CORNER_TURBO>;
>  						};
>  						rpmpd_opp_super_turbo: opp6 {
> -							opp-level = <6>;
> +							opp-level = <RPM_SMD_CORNER_SUPER_TURBO>;

See comment on previous patch, I think it's fine to stick with the
numerical values here, as the label gives them meaning to the clients.

>  						};
>  					};
>  				};
> @@ -933,6 +933,8 @@ gcc: clock-controller@1800000 {
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
> +			power-domains = <&rpmpd MSM8916_VDDCX>;
> +			power-domain-names = "vdd";

This makes sense even without your patches, as it creates a relationship
between gdscs of the clock-controller and VDDCX - such that enable and
performance state of the gdscs propagates up to VDDCX.

Could you please check that this seems to work properly?


PS. We don't need power-domain-names.

Regards,
Bjorn

>  			reg = <0x01800000 0x80000>;
>  		};
>  
> -- 
> 2.25.1
>