Re: [PATCH 04/11] clk: qcom: gcc-msm8974: move clock parent tables down

Neil Armstrong
2022-09-28T15:24:30Z

On 28/09/2022 16:59, Dmitry Baryshkov wrote:
> Move clock parent tables down, after the PLL declrataions, so that we
typo: s/declrataions/declarations/
> can use pll hw clock fields in the next commit.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++-----------------
> 1 file changed, 49 insertions(+), 49 deletions(-)

<snip

> +static struct clk_pll gpll4 = {
> + .l_reg = 0x1dc4,
> + .m_reg = 0x1dc8,
> + .n_reg = 0x1dcc,
> + .config_reg = 0x1dd4,
> + .mode_reg = 0x1dc0,
> + .status_reg = 0x1ddc,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll4",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap gpll4_vote = {
> + .enable_reg = 0x1480,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll4_vote",
> + .parent_names = (const char *[]){ "gpll4" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +

<snip>

>
> -static struct clk_pll gpll4 = {
> - .l_reg = 0x1dc4,
> - .m_reg = 0x1dc8,
> - .n_reg = 0x1dcc,
> - .config_reg = 0x1dd4,
> - .mode_reg = 0x1dc0,
> - .status_reg = 0x1ddc,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "gpll4",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap gpll4_vote = {
> - .enable_reg = 0x1480,
> - .enable_mask = BIT(4),
> - .hw.init = &(struct clk_init_data){
> - .name = "gpll4_vote",
> - .parent_names = (const char *[]){ "gpll4" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};

<snip>

nitpick: you're also moving pll4 up, it's worth adding it to commit message

Neil