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In-Reply-To: <cover.1665147497.git.geert+renesas@glider.be>
References: <cover.1665147497.git.geert+renesas@glider.be>
Subject: Re: [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
        linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
        Geert Uytterhoeven <geert+renesas@glider.be>
To:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Michael Turquette <mturquette@baylibre.com>
Date:   Fri, 07 Oct 2022 13:47:06 -0700
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Quoting Geert Uytterhoeven (2022-10-07 06:09:59)
>         Hi Mike, Stephen,
>=20
> This patch series adds the various SASYNCPER clocks (used by modules
> that must not be affected by Spread Spectrum and/or Fractional
> Multiplication), and most of its derived module clocks (serial and PWM)
> on the R-Car V4H (R8A7799G0) SoC.
>=20
> As the second patch is a fix, and the first patch is a dependency (also
> for a related DT fix), I plan to queue the first two patches in
> renesas-clk-fixes for v6.1.
> I plan to queue the last three patches in renesas-clk for v6.2.
>=20
> Thanks for your comments!
>=20
> Geert Uytterhoeven (5):
>   clk: renesas: r8a779g0: Add SASYNCPER clocks
>   clk: renesas: r8a779g0: Fix HSCIF parent clocks
>   clk: renesas: r8a779g0: Add SCIF clocks
>   clk: renesas: r8a779g0: Add PWM clock
>   clk: renesas: r8a779g0: Add TPU clock
>=20

Thanks for the heads up

Acked-by: Stephen Boyd <sboyd@kernel.org>