Linux clock framework development
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From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: "Maxime Ripard" <maxime@cerno.tech>,
	"Noralf Trønnes" <noralf@tronnes.org>,
	"Stefan Wahren" <stefan.wahren@i2se.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Sasha Levin" <sashal@kernel.org>,
	mturquette@baylibre.com, f.fainelli@gmail.com, rjui@broadcom.com,
	sbranden@broadcom.com, nsaenz@kernel.org, iivanov@suse.de,
	linux-clk@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH AUTOSEL 6.0 66/67] clk: bcm2835: Make peripheral PLLC critical
Date: Wed, 12 Oct 2022 20:15:47 -0400	[thread overview]
Message-ID: <20221013001554.1892206-66-sashal@kernel.org> (raw)
In-Reply-To: <20221013001554.1892206-1-sashal@kernel.org>

From: Maxime Ripard <maxime@cerno.tech>

[ Upstream commit 6c5422851d8be8c7451e968fd2e6da41b6109e17 ]

When testing for a series affecting the VEC, it was discovered that
turning off and on the VEC clock is crashing the system.

It turns out that, when disabling the VEC clock, it's the only child of
the PLLC-per clock which will also get disabled. The source of the crash
is PLLC-per being disabled.

It's likely that some other device might not take a clock reference that
it actually needs, but it's unclear which at this point. Let's make
PLLC-per critical so that we don't have that crash.

Reported-by: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220926084509.12233-1-maxime@cerno.tech
Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Noralf Trønnes <noralf@tronnes.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/clk/bcm/clk-bcm2835.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 48a1eb9f2d55..19de0e83b65d 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1784,7 +1784,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.load_mask = CM_PLLC_LOADPER,
 		.hold_mask = CM_PLLC_HOLDPER,
 		.fixed_divider = 1,
-		.flags = CLK_SET_RATE_PARENT),
+		.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 
 	/*
 	 * PLLD is the display PLL, used to drive DSI display panels.
-- 
2.35.1


  parent reply	other threads:[~2022-10-13  0:23 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20221013001554.1892206-1-sashal@kernel.org>
2022-10-13  0:14 ` [PATCH AUTOSEL 6.0 02/67] clk: zynqmp: Fix stack-out-of-bounds in strncpy` Sasha Levin
2022-10-13  0:14 ` [PATCH AUTOSEL 6.0 05/67] clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate Sasha Levin
2022-10-13  0:15 ` [PATCH AUTOSEL 6.0 20/67] clk: microchip: mpfs: add MSS pll's set & round rate Sasha Levin
2022-10-13  5:29   ` Conor Dooley
2022-10-13 17:55     ` Sasha Levin
2022-10-13  0:15 ` Sasha Levin [this message]
2022-10-13  0:15 ` [PATCH AUTOSEL 6.0 67/67] clk: bcm2835: Round UART input clock up Sasha Levin

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