Re: [PATCH 11/13] clk: qcom: cpu-8996: fix PLL clock ops

Dmitry Baryshkov
2023-01-13T11:44:44Z

On 12/01/2023 18:10, Konrad Dybcio wrote:
>
>
> On 11.01.2023 20:20, Dmitry Baryshkov wrote:
>> Switch CPU PLLs to use clk_alpha_pll_hwfsm_ops, it seems to suit
>> better.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> I *think* SUPPORTS_DYNAMIC_UPDATE should also be kicked from
> non-alt PLLs.. Otherwise we might have been kicking ourselves
> in the face all along, changing the frequency of a running
> PLL that doesn't support it if we were using the main PLL
> and not the altPLL/ACD..
>
> Downstream sets it only for clk_ops_alpha_pll_hwfsm which is
> used on alt PLLs only
>
> This change seems sound, as Huayra supports dynamic update
> even without setting any flags.

I don't know where Huayra came from. Downstream uses plain hwfsm pll.
Huayra uses different alpha register settings.

>
> Konrad
>> drivers/clk/qcom/clk-cpu-8996.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
>> index 1c00eb629b61..b53cddc4bca3 100644
>> --- a/drivers/clk/qcom/clk-cpu-8996.c
>> +++ b/drivers/clk/qcom/clk-cpu-8996.c
>> @@ -128,7 +128,7 @@ static struct clk_alpha_pll pwrcl_pll = {
>> .name = "pwrcl_pll",
>> .parent_data = pll_parent,
>> .num_parents = ARRAY_SIZE(pll_parent),
>> - .ops = &clk_alpha_pll_huayra_ops,
>> + .ops = &clk_alpha_pll_hwfsm_ops,
>> },
>> };
>>
>> @@ -140,7 +140,7 @@ static struct clk_alpha_pll perfcl_pll = {
>> .name = "perfcl_pll",
>> .parent_data = pll_parent,
>> .num_parents = ARRAY_SIZE(pll_parent),
>> - .ops = &clk_alpha_pll_huayra_ops,
>> + .ops = &clk_alpha_pll_hwfsm_ops,
>> },
>> };
>>

--
With best wishes
Dmitry