From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD6A4C7EE32 for ; Tue, 28 Feb 2023 09:16:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229673AbjB1JQz (ORCPT ); Tue, 28 Feb 2023 04:16:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229565AbjB1JQx (ORCPT ); Tue, 28 Feb 2023 04:16:53 -0500 Received: from codeconstruct.com.au (pi.codeconstruct.com.au [203.29.241.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3C762BEEB; Tue, 28 Feb 2023 01:16:51 -0800 (PST) Received: by codeconstruct.com.au (Postfix, from userid 10000) id E1E6C20261; Tue, 28 Feb 2023 17:16:47 +0800 (AWST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1677575807; bh=Nmn4HH5803cy07yWAH0sQPYtbLPgpmt7KgYyu56Yn9I=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=OYxKrpQvKxvIE9YPqFaGG4ql/yBd42fGVqUE5A3Lj8QC/6ya1j0LGmw+wbJXNPIcg aTkQRiMzA2XJMOmo6kFsv6U4I8QJK4B86NTTeaaKD71+rwxF9s9i06gsNeF0v5JHdD 3OjaU98nLNJSuEwed1DL5pmhVj9g58eI9EObmiytO9Xe9QOF+nE547+CLnthcflyUU hrc8r3bWR5UwjC6HA94uXk1Ei9/J5KL4BflYrhozDmxIFWaVcb3v9FzzKV+j+QGXO4 GGozlWeXY4Z51cDxsyLQK2THQz9VGJCh0vfZqxx6eDhxz/ZFZp+e+CmckU9fbpqigV YidDv0aU7CaUA== From: Jeremy Kerr To: linux-aspeed@lists.ozlabs.org, linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski , Michael Turquette , Rob Herring , Stephen Boyd , Dylan Hung , Joel Stanley , Andrew Jeffery Subject: [PATCH v4 2/5] dt-bindings: clock: ast2600: Add top-level I3C clock Date: Tue, 28 Feb 2023 17:16:35 +0800 Message-Id: <20230228091638.206569-3-jk@codeconstruct.com.au> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230228091638.206569-1-jk@codeconstruct.com.au> References: <20230228091638.206569-1-jk@codeconstruct.com.au> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The ast2600 hardware has a top-level clock for all i3c controller peripherals (then gated to each individual controller), so add a top-level i3c clock line to control this. This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7 from Aspeed's own tree, originally by Dylan Hung . Signed-off-by: Jeremy Kerr --- v4: - use contiguous clock index v3: - split into separate bindings & clk changes v2: - reword commit message --- include/dt-bindings/clock/ast2600-clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index d8b0db2f7a7d..dd1581bfdf58 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -87,6 +87,7 @@ #define ASPEED_CLK_MAC2RCLK 68 #define ASPEED_CLK_MAC3RCLK 69 #define ASPEED_CLK_MAC4RCLK 70 +#define ASPEED_CLK_I3C 71 /* Only list resets here that are not part of a gate */ #define ASPEED_RESET_ADC 55 -- 2.39.1