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Date: Sat, 16 Dec 2023 12:26:02 +0000
From: Conor Dooley <conor@kernel.org>
To: Zhifeng Tang <zhifeng.tang@unisoc.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Orson Zhai <orsonzhai@gmail.com>,
	Baolin Wang <baolin.wang@linux.alibaba.com>,
	Chunyan Zhang <zhang.lyra@gmail.com>, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Zhifeng Tang <zhifeng.tang23@gmail.com>,
	Wenming Wu <wenming.wu@unisoc.com>
Subject: Re: [PATCH 4/4] dt-bindings: clock: Add reset controller bindings
 for Unisoc's UMS512.
Message-ID: <20231216-service-gallows-797dea781edb@spud>
References: <20231215081003.8373-1-zhifeng.tang@unisoc.com>
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On Fri, Dec 15, 2023 at 04:10:03PM +0800, Zhifeng Tang wrote:
> Add Reset Controller bindings to clock bindings for Unisoc's UMS512.

This is what the diff is doing, but there's no justification for why
this is the case. I _assume_ that the clock controller register block
also contains reset bits for some of these peripherals, but the commit
message needs to say that.

Cheers,
Conor.

>=20
> Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com>
> ---
>  Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml | 3 +++
>  1 file changed, 3 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml=
 b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> index 43d2b6c31357..6b0892d637fe 100644
> --- a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> @@ -34,6 +34,9 @@ properties:
>    "#clock-cells":
>      const: 1
> =20
> +  "#reset-cells":
> +    const: 1
> +
>    clocks:
>      minItems: 1
>      maxItems: 4
> --=20
> 2.17.1
>=20

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