From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BEC37D60B; Mon, 18 Dec 2023 12:44:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GUaMLsN0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 187A2C433C7; Mon, 18 Dec 2023 12:44:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702903459; bh=lLy/lC6aZ8f1isiXe0PcaE037D+ZGlj/4j45v8Ta0qo=; h=From:To:Cc:Subject:Date:From; b=GUaMLsN0m5OIuelaAONBu3IvMpNSDCvHu42EBPo9vpetSI6Ae0OKEUyUwHAMLwaEW boHcefgWiByDVKSCS2m6MXhDaND5WPHdekjOYF+mPArwDgb0U0RiRffRGU/Sd0Zz7h eh4TejTpz24QojlTT8AkKX/MEwx7cHIcbk81VdiVOOYnJOCHpfng8uF1P+WVp/PIMG eJ6+ABvnbif8H5MNjxRZBmzc6DJHecT2bwCxCEG2vdK5mZ9ZsB27S14Sz8HDCWCPJ+ y4PLyLLq+dA9CgR6MMGybdmcAYHRFzoE01OFvieQa+invMcjxoQ2ye4b0lJZf60VDz +t6ycezZ5t4sA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Chris Morgan , Heiko Stuebner , Sasha Levin , mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH AUTOSEL 6.6 01/18] clk: rockchip: rk3568: Add PLL rate for 292.5MHz Date: Mon, 18 Dec 2023 07:43:35 -0500 Message-ID: <20231218124415.1379060-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.6.7 Content-Transfer-Encoding: 8bit From: Chris Morgan [ Upstream commit 1af27671f62ce919f1fb76082ed81f71cb090989 ] Add support for a PLL rate of 292.5MHz so that the Powkiddy RGB30 panel can run at a requested 60hz (59.96, close enough). I have confirmed this rate fits with all the constraints listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter 2 Clock & Reset Unit (CRU)." Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20231018153357.343142-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin --- drivers/clk/rockchip/clk-rk3568.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 16dabe2b9c47f..db713e1526cdc 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -72,6 +72,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0), RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), -- 2.43.0