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AJvYcCV+Qou93dzXsJKngzmdFtc+AM23Mdmca4TdmigGzQiQDI0THN6tRGxjkz73+JDyBaD6wjDwNLmQGllGfRwgaWzLnyK+JNRIYWW2 X-Gm-Message-State: AOJu0Yypy6c8awTMhNgg8YF8Wy/s1/BSLt8dV7fdnxKKVQvM8tNXW+y+ nei9URJR/0FtNmTOXj/JBMSDvBhOfoV0ooyfO7QdrsosUrZkh79UB4FtGJpc3g== X-Google-Smtp-Source: AGHT+IHaHrm2pb+wT7KKfQkSKKuzy7HKCVhCIyuFy2rzef2uOrb0UaXT1cyILAlN1opmVB/oaR6cAg== X-Received: by 2002:a05:6870:70a1:b0:22f:70da:1f26 with SMTP id v33-20020a05687070a100b0022f70da1f26mr19032069oae.27.1713338054787; Wed, 17 Apr 2024 00:14:14 -0700 (PDT) Received: from thinkpad ([120.60.54.9]) by smtp.gmail.com with ESMTPSA id z3-20020aa78883000000b006e5571be110sm9998837pfe.214.2024.04.17.00.14.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 00:14:14 -0700 (PDT) Date: Wed, 17 Apr 2024 12:44:06 +0530 From: Manivannan Sadhasivam To: Alexandru Gagniuc Cc: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v3 4/7] PCI: qcom: Add support for IPQ9574 Message-ID: <20240417071406.GC3894@thinkpad> References: <20240415182052.374494-1-mr.nuke.me@gmail.com> <20240415182052.374494-5-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240415182052.374494-5-mr.nuke.me@gmail.com> On Mon, Apr 15, 2024 at 01:20:49PM -0500, Alexandru Gagniuc wrote: > Add support for the PCIe on IPQ9574. The main difference from ipq6018 > is that the "iface" clock is not necessarry. Add a special case in > qcom_pcie_get_resources_2_9_0() to handle this. > Could you add more information about the PCIe controller used in this SoC? Like controller version, supported data rate, PCIe generation etc... - Mani > Signed-off-by: Alexandru Gagniuc > --- > drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 14772edcf0d3..10560d6d6336 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1101,15 +1101,19 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) > struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; > struct dw_pcie *pci = pcie->pci; > struct device *dev = pci->dev; > - int ret; > + int ret, num_clks = ARRAY_SIZE(res->clks) - 1; > > - res->clks[0].id = "iface"; > + res->clks[0].id = "rchng"; > res->clks[1].id = "axi_m"; > res->clks[2].id = "axi_s"; > res->clks[3].id = "axi_bridge"; > - res->clks[4].id = "rchng"; > > - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); > + if (!of_device_is_compatible(dev->of_node, "qcom,pcie-ipq9574")) { > + res->clks[4].id = "iface"; > + num_clks++; > + } > + > + ret = devm_clk_bulk_get(dev, num_clks, res->clks); > if (ret < 0) > return ret; > > @@ -1664,6 +1668,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, > { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, > { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, > + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 }, > { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, > { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, > { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, > -- > 2.40.1 > -- மணிவண்ணன் சதாசிவம்