Re: [PATCH v4 RESEND 0/8] ipq9574: Enable PCI-Express support

Krzysztof Kozlowski
2024-05-01T10:22:51Z

On 01/05/2024 06:28, Alexandru Gagniuc wrote:
> There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series
> addresses pcie2, which is a gen3x2 port. The board I have only uses
> pcie2, and that's the only one enabled in this series. pcie3 is added
> as a special request, but is untested.
>
> I believe this makes sense as a monolithic series, as the individual
> pieces are not that useful by themselves.
>
> In v2, I've had some issues regarding the dt schema checks. For
> transparency, I used the following test invocations to test:
>
> make dt_binding_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
> make dtbs_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml
>
> Changes since v3:
> - "const"ify .hw.init fields for the PCIE pipe clocks
> - Used pciephy_v5_regs_layout instead of v4 in phy-qcom-qmp-pcie.c
> - Included Manivannan's patch for qcom-pcie.c clocks
> - Dropped redundant comments in "ranges" and "interrupt-map" of pcie2.
> - Added pcie3 and pcie3_phy dts nodes
> - Moved snoc and anoc clocks to PCIe controller from PHY
>

Three postings within short time... Allow people to actually review your
code. Please wait 24h before posting new version. Include entire
feedback and all tags. Explain why you ignore/skip some tags.

Best regards,
Krzysztof