RE: [PATCH v5 0/2] Add notifier for PLL0 clock and set it 1.5GHz on

Xingyu Wu
2024-05-11T07:37:04Z

On 11/05/2024 05:05, Conor Dooley wrote:
>
> On Tue, May 07, 2024 at 02:53:17PM +0800, Xingyu Wu wrote:
> > This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
> >
> > The first patch is to add the notifier for PLL0 clock. Setting the
> > PLL0 rate need the son clock (cpu_root) to switch its parent clock to
> > OSC clock and switch it back after setting PLL0 rate. It need to use
> > the cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> > driver.
> >
> > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
> > 1.5GHz to fix the problem about the lower rate of CPUfreq on the
> > visionfive board. The cpu_core clock rate is set to 500MHz first to
> > ensure that the cpu frequency will not suddenly become high and the
> > cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
> > The cpu voltage and frequency are then adjusted together by CPUfreq.
>
> Hmm, how does sequencing work here? If we split the patches between trees it
> sounds like without the dts patch, the clock tree would (or
> could) crash, or mainline if the clock changes there before the dts ones do. Am I
> misunderstanding that?

Oh, I think you misunderstood it. Patch 1 (clock driver patch) does not cause the
clock tree crash without the patch 2 (dts patch), and it just provides the correct
flow of how to change the PLL0 rate. The patch 2 is to set the clock rate of
cpu_core and PLL0 rate, which causes the crash without patch 1. Setting cpu_core
rate is to avoid crashes by insufficient cpu voltage when setting PLL0 rate.

Best regards,
Xingyu Wu