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[83.135.56.50]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e801d66f6sm55926815e9.29.2024.09.22.10.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Sep 2024 10:09:27 -0700 (PDT) Date: Sun, 22 Sep 2024 19:09:25 +0200 From: Manivannan Sadhasivam To: Qiang Yu Cc: Krishna Chaitanya Chundru , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v2 0/5] Add support for PCIe3 on x1e80100 Message-ID: <20240922170925.qcuwja6oaqlbng5j@thinkpad> References: <20240913083724.1217691-1-quic_qianyu@quicinc.com> <36bd9f69-e263-08a1-af07-45185ea03671@quicinc.com> <6f1118eb-89cf-4fd4-a35d-e8b98b0b7a8d@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <6f1118eb-89cf-4fd4-a35d-e8b98b0b7a8d@quicinc.com> On Thu, Sep 19, 2024 at 10:14:06PM +0800, Qiang Yu wrote: > > On 9/14/2024 11:59 AM, Krishna Chaitanya Chundru wrote: > > Hi qiang, > > > > In next series can you add logic in controller driver > > to have new ops for this x1e80100 since this hardware > > has smmuv3 support but currently the ops_1_9_0 ops which > > is being used has configuring bdf to sid table which will > > be not present for this devices. > > > Sure, bdf2sid map is not supported and required since we use smmuv3 for > pcie on x1e80100. Can I add a new ops which is same as ops_1_9_0 basically > and only config_sid callback is removed. Or add a new flag to determine if > we need to config bdf2sid map like no_l0s. > > Hi Mani, what do you think about this? > Good question. IMO it is better to add a new ops even though it duplictes the callbacks. Because the newer platforms are not going to need this bdf2sid map anyway. But if we add a flag to determine that, then the check will become, if (pcie->cfg->ops->config_sid && !pcie->cfg->smmuv3) ... And this doesn't look good as both conditions are false for X1E80100 i.e., it doesn't need bdf2sid mapping and it is also a SMMUv3 platform. Moreover having two checks here makes it confusing also. So let's use a new callback. But please mention the IP revision in comments as like other ops. - Mani > Thanks, > Qiang > > > > - Krishna Chaitanya. > > > > On 9/13/2024 2:07 PM, Qiang Yu wrote: > > > This series add support for PCIe3 on x1e80100. > > > > > > PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP > > > PHY configuration compare other PCIe instances on x1e80100. Hence add > > > required resource configuration and usage for PCIe3. > > > > > > v2->v1: > > > 1. Squash [PATCH 1/8], [PATCH 2/8],[PATCH 3/8] into one patch and > > > make the > > >     indentation consistent. > > > 2. Put dts patch at the end of the patchset. > > > 3. Put dt-binding patch at the first of the patchset. > > > 4. Add a new patch where opp-table is added in dt-binding to avoid dtbs > > >     checking error. > > > 5. Remove GCC_PCIE_3_AUX_CLK, RPMH_CXO_CLK, put in > > > TCSR_PCIE_8L_CLKREF_EN > > >     as ref. > > > 6. Remove lane_broadcasting. > > > 7. Add 64 bit bar, Remove GCC_PCIE_3_PIPE_CLK_SRC, > > >     GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK is changed to > > >     GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK. > > > 8. Add Reviewed-by tag. > > > 9. Remove [PATCH 7/8], [PATCH 8/8]. > > > > > > Qiang Yu (5): > > >    dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 > > >      QMP PCIe PHY Gen4 x8 > > >    dt-bindings: PCI: qcom: Add OPP table for X1E80100 > > >    phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 > > >    clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks > > >    arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 > > > > > >   .../bindings/pci/qcom,pcie-x1e80100.yaml      |   4 + > > >   .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml       |   3 + > > >   arch/arm64/boot/dts/qcom/x1e80100.dtsi        | 202 ++++++++++++++++- > > >   drivers/clk/qcom/gcc-x1e80100.c               |  10 +- > > >   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 211 ++++++++++++++++++ > > >   .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h    |  25 +++ > > >   drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h |  19 ++ > > >   7 files changed, 468 insertions(+), 6 deletions(-) > > >   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h > > >   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h > > > -- மணிவண்ணன் சதாசிவம்