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b=ZMcQewpjew4EGWseaDIabpzeFj3eQ8ky1BYh35ijVN8a9ywaYOzOLW5aJ8B4+zDRM CsKSUr7uDb5euSsYbjhqp/7Rj4h/tyLzoHrsMuf+tctX+WWcqSOxIMPAA1WbS1D+N/ NOkXtCxPoJGby5mN8LSjJ3IQ8Mh0uJFrLIZO6qNE= Date: Mon, 9 Dec 2024 23:40:35 +0200 From: Laurent Pinchart To: Geert Uytterhoeven Cc: Tomi Valkeinen , Kieran Bingham , Andrzej Hajda , Neil Armstrong , Robert Foss , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , LUU HOAI , Jagan Teki , Sam Ravnborg , Biju Das , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Tomi Valkeinen Subject: Re: [PATCH v3 05/10] clk: renesas: r8a779h0: Add display clocks Message-ID: <20241209214035.GB26531@pendragon.ideasonboard.com> References: <20241206-rcar-gh-dsi-v3-0-d74c2166fa15@ideasonboard.com> <20241206-rcar-gh-dsi-v3-5-d74c2166fa15@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Dec 09, 2024 at 08:49:18AM +0100, Geert Uytterhoeven wrote: > On Mon, Dec 9, 2024 at 6:26 AM Tomi Valkeinen wrote: > > On 06/12/2024 15:43, Geert Uytterhoeven wrote: > > > On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen wrote: > > >> From: Tomi Valkeinen > > >> > > >> Add display related clocks for DU, DSI, FCPVD, and VSPD. > > >> > > >> Signed-off-by: Tomi Valkeinen > > >> Reviewed-by: Laurent Pinchart > > >> Tested-by: Geert Uytterhoeven > > > > > > Reviewed-by: Geert Uytterhoeven > > > i.e. will queue in renesas-clk for v6.14. > > > > > >> --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > >> +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > >> @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > > >> DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), > > >> DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), > > >> DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), > > >> + DEF_MOD("dis0", 411, R8A779H0_CLK_S0D3), > > >> + DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_DSIREF), > > >> + DEF_MOD("fcpvd0", 508, R8A779H0_CLK_S0D3), > > >> DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), > > >> DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), > > >> DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), > > >> @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > > >> DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), > > >> DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), > > >> DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), > > >> + DEF_MOD("vspd0", 830, R8A779H0_CLK_S0D1_VIO), > > >> DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), > > >> DEF_MOD("cmt0", 910, R8A779H0_CLK_R), > > >> DEF_MOD("cmt1", 911, R8A779H0_CLK_R), > > > > > > As mentioned by Laurent during his review on v1, all clock parents > > > should probably be some form of R8A779H0_CLK_S0Dx_VIO. > > > So I'm inclined to replace all of them by R8A779H0_CLK_VIOBUSD2 while > > > applying, which would match R-Car V4H. > > > > What do you mean with the above? First you say the clock parents should > > be some form of S0Dx_VIO, but then you say you'll use VIOBUSD2. Aren't > > those unrelated clocks, from different PLLs? > > Oops, copy-'n-paste went wrong. I did mean R8A779H0_VIOBUSD*. > > > > Are you OK with that? > > > > I'm fine with that. I can't really get much out of the docs wrt. > > clocking, and the clocks I used were from the BSP. Afaics, it looks > > similar to V4H, so it's probably best have the same clocks, as you suggest. > > Agreed. Works for me too. -- Regards, Laurent Pinchart