From: Rohit Visavalia <rohit.visavalia@amd.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<michal.simek@amd.com>, <vishal.sagar@amd.com>
Cc: <javier.carrasco.cruz@gmail.com>, <geert+renesas@glider.be>,
<u.kleine-koenig@baylibre.com>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Rohit Visavalia <rohit.visavalia@amd.com>
Subject: [PATCH v2 2/3] clk: xilinx: vcu: don't set pll_ref as parent of VCU(enc/dec) clocks
Date: Thu, 2 Jan 2025 09:03:58 -0800 [thread overview]
Message-ID: <20250102170359.761670-3-rohit.visavalia@amd.com> (raw)
In-Reply-To: <20250102170359.761670-1-rohit.visavalia@amd.com>
CCF will try to adjust parent clock to set desire clock frequency of
child clock. So if pll_ref is not a fixed-clock then while setting rate
of enc/dec clocks pll_ref may get change, which may make VCU malfunction.
Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
---
Changes in v2:
- none
- Link to v1: https://lore.kernel.org/linux-clk/20241226122023.3439559-3-rohit.visavalia@amd.com
---
drivers/clk/xilinx/xlnx_vcu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c
index 88b3fd8250c2..c520ae1ba65e 100644
--- a/drivers/clk/xilinx/xlnx_vcu.c
+++ b/drivers/clk/xilinx/xlnx_vcu.c
@@ -547,7 +547,7 @@ static int xvcu_register_clock_provider(struct xvcu_device *xvcu)
return PTR_ERR(hw);
xvcu->pll_post = hw;
- parent_data[0].fw_name = "pll_ref";
+ parent_data[0].fw_name = "dummy_name";
parent_data[1].hw = xvcu->pll_post;
hws[CLK_XVCU_ENC_CORE] =
--
2.25.1
next prev parent reply other threads:[~2025-01-02 17:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-02 17:03 [PATCH v2 0/3] clk: xilinx: vcu: Sequence update and couple of fixes Rohit Visavalia
2025-01-02 17:03 ` [PATCH v2 1/3] clk: xilinx: vcu: unregister pll_post only if registered correctly Rohit Visavalia
2025-01-02 17:03 ` Rohit Visavalia [this message]
2025-01-02 19:28 ` [PATCH v2 2/3] clk: xilinx: vcu: don't set pll_ref as parent of VCU(enc/dec) clocks Geert Uytterhoeven
2025-01-06 10:04 ` Visavalia, Rohit
2025-01-28 9:54 ` Visavalia, Rohit
2025-01-02 17:03 ` [PATCH v2 3/3] clk: xilinx: vcu: Update vcu init/reset sequence Rohit Visavalia
2025-01-02 19:30 ` Geert Uytterhoeven
2025-01-06 10:04 ` Visavalia, Rohit
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