From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AA24723245B; Tue, 14 Jan 2025 16:00:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736870455; cv=none; b=mVrUBfaYbE7hsFIV4qwVkPXVanrO1Ysc4ipEqjVLYD4D6eQ62T3PrpZB/oJuoXTxSQnm/p4s/hUKltFK9Yx575xVp8Ybgf4Eu58p3cJywENXYY5e6mTSf7gzmiFtJs47UTFV+bafWZSObl8uvO9GSRjpUJe6Dk/ePmmvKgpFq6E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736870455; c=relaxed/simple; bh=aWfKJEabF6fhYzlM/VczVohRgjerSXRLXxXHniHZnZ4=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WWYNl6wZoKX8C/vItVgHdNcyWdmr7M6acO5iZjr/9UVH6ZrvndANSyibV/yIfHkM6JgzuAEAcG2Cb7mTcURCshW58eUK5qz1GAWHFV0F6wUbUTRJCzcrasFA3UtHZauNVCy/oZCFeLP6s6bc1D9QOaInyDuXBLY+6OTfQeDSIC8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68F4C11FB; Tue, 14 Jan 2025 08:01:21 -0800 (PST) Received: from donnerap.manchester.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2A3A23F673; Tue, 14 Jan 2025 08:00:48 -0800 (PST) Date: Tue, 14 Jan 2025 16:00:45 +0000 From: Andre Przywara To: Parthiban Nallathambi Cc: Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij , Vinod Koul , Kishon Vijay Abraham I , iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH RESEND 10/22] pinctrl: sunxi: add missed lvds pins for a100/a133 Message-ID: <20250114160045.2baacdaa@donnerap.manchester.arm.com> In-Reply-To: <20241227-a133-display-support-v1-10-abad35b3579c@linumiz.com> References: <20241227-a133-display-support-v1-0-abad35b3579c@linumiz.com> <20241227-a133-display-support-v1-10-abad35b3579c@linumiz.com> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 27 Dec 2024 18:30:59 +0530 Parthiban Nallathambi wrote: Hi, since LinusW wants to pull this already, I gave it a look, despite this series being not complete. > lvds, lcd, dsi all shares the same GPIO D bank and lvds0 > data 3 lines and lvds1 pins are missed, add them. > > Signed-off-by: Parthiban Nallathambi > --- > drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c > index df90c75fb3c5..b97de80ae2f3 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c > @@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = { > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ > + SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */ I initially stumbled upon those first two pins being from lvds0, with the other 8 pins missing for this interface, but then realised that those are on portD, and we already describe them in this table (above). So those two were missing all the time. So having compared these lines to the A133 user manual, I can now say that they are all correct: Reviewed-by: Andre Przywara Linus, in contrast to what I originally thought, this patch *is* fine, so feel free to keep it in your tree. Sorry for the noise! Cheers, Andre > SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ > + SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */ > SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */ > SUNXI_FUNCTION(0x4, "spi1"), /* CS */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */ > SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */ > SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */ > SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */ > SUNXI_FUNCTION(0x4, "uart3"), /* TX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */ > SUNXI_FUNCTION(0x4, "uart3"), /* RX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */ > SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */ > SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D3P */ > SUNXI_FUNCTION(0x4, "uart4"), /* TX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), > SUNXI_FUNCTION(0x0, "gpio_in"), > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ > + SUNXI_FUNCTION(0x3, "lvds1"), /* D3N */ > SUNXI_FUNCTION(0x4, "uart4"), /* RX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), > SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), >