From: Yao Zi <ziyao@disroot.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
Yao Zi <ziyao@disroot.org>
Subject: [PATCH v3 5/5] arm64: dts: rockchip: Add UART clocks for RK3528 SoC
Date: Mon, 17 Feb 2025 06:11:46 +0000 [thread overview]
Message-ID: <20250217061142.38480-10-ziyao@disroot.org> (raw)
In-Reply-To: <20250217061142.38480-5-ziyao@disroot.org>
Add missing clocks in UART nodes for RK3528 SoC.
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 37fd40377076..5b334690356a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -168,7 +168,8 @@ cru: clock-controller@ff4a0000 {
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
- clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -178,6 +179,8 @@ uart0: serial@ff9f0000 {
uart1: serial@ff9f8000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f8000 0x0 0x100>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -187,6 +190,8 @@ uart1: serial@ff9f8000 {
uart2: serial@ffa00000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa00000 0x0 0x100>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -195,6 +200,8 @@ uart2: serial@ffa00000 {
uart3: serial@ffa08000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
reg = <0x0 0xffa08000 0x0 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -204,6 +211,8 @@ uart3: serial@ffa08000 {
uart4: serial@ffa10000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa10000 0x0 0x100>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -213,6 +222,8 @@ uart4: serial@ffa10000 {
uart5: serial@ffa18000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa18000 0x0 0x100>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -222,6 +233,8 @@ uart5: serial@ffa18000 {
uart6: serial@ffa20000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa20000 0x0 0x100>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -231,6 +244,8 @@ uart6: serial@ffa20000 {
uart7: serial@ffa28000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa28000 0x0 0x100>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
--
2.48.1
next prev parent reply other threads:[~2025-02-17 6:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 6:11 [PATCH v3 0/5] Support clock and reset unit of Rockchip RK3528 Yao Zi
2025-02-17 6:11 ` [PATCH v3 1/5] dt-bindings: clock: Document clock and reset unit of RK3528 Yao Zi
2025-02-17 11:16 ` Krzysztof Kozlowski
2025-02-24 9:09 ` Heiko Stübner
2025-02-24 17:35 ` Yao Zi
2025-02-17 6:11 ` [PATCH v3 2/5] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE Yao Zi
2025-02-17 6:11 ` [PATCH v3 3/5] clk: rockchip: Add clock controller driver for RK3528 SoC Yao Zi
2025-02-17 6:11 ` [PATCH v3 4/5] arm64: dts: rockchip: Add clock generators " Yao Zi
2025-02-17 6:11 ` Yao Zi [this message]
2025-02-26 19:49 ` [PATCH v3 0/5] Support clock and reset unit of Rockchip RK3528 Heiko Stuebner
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